/openbmc/linux/arch/arm64/boot/dts/allwinner/ |
H A D | sun50i-h5.dtsi | 11 #size-cells = <0>; 13 cpu0: cpu@0 { 16 reg = <0>; 84 reg = <0x01c00000 0x1000>; 91 reg = <0x00018000 0x1c000>; 94 ranges = <0 0x00018000 0x1c000>; 96 ve_sram: sram-section@0 { 99 reg = <0x000000 0x1c000>; 106 reg = <0x01c0e000 0x1000>; 117 reg = <0x01c15000 0x1000>; [all …]
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/openbmc/linux/drivers/clk/qcom/ |
H A D | q6sstop-qcs404.c | 23 .halt_reg = 0x1b004, 26 .enable_reg = 0x1b004, 27 .enable_mask = BIT(0), 36 .halt_reg = 0x22000, 39 .enable_reg = 0x22000, 40 .enable_mask = BIT(0), 49 .halt_reg = 0x1c000, 52 .enable_reg = 0x1c000, 53 .enable_mask = BIT(0), 62 .halt_reg = 0x22004, [all …]
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/openbmc/qemu/tests/qemu-iotests/ |
H A D | 046 | 25 seq=`basename $0` 34 trap "_cleanup; exit \$status" 0 1 2 3 15 60 local pattern=0 61 local cur_sec=0 63 for ((i=0;i<=$((sectors - 1));i++)); do 71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io 84 aio_write -P 10 0x18000 0x2000 87 aio_write -P 11 0x12000 0x2000 88 aio_write -P 12 0x1c000 0x2000 98 aio_write -P 20 0x28000 0x2000 [all …]
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/openbmc/linux/arch/mips/include/asm/mach-ip27/ |
H A D | kernel-entry-init.h | 30 * This needs to read the nasid - assume 0 for now. 31 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, 32 * 0+DVG in tlblo_1. 34 dli t0, 0xffffffffc0000000 36 li t0, 0x1c000 # Offset of text into node memory 51 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M 53 li t0, 0 # KMAP_INX 82 ld t0, 0(t0) # t0 points to kern_vars struct 91 PTR_LA t0, 0f 93 0:
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/openbmc/u-boot/include/configs/ |
H A D | ls1021aqds.h | 54 #define CONFIG_SPL_TEXT_BASE 0x10000000 55 #define CONFIG_SPL_MAX_SIZE 0x1a000 56 #define CONFIG_SPL_STACK 0x1001d000 57 #define CONFIG_SPL_PAD_TO 0x1c000 61 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 62 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 64 #define CONFIG_SYS_MONITOR_LEN 0xc0000 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x1a000 [all …]
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H A D | ls1021aiot.h | 28 #define DDR_SDRAM_CFG 0x470c0008 29 #define DDR_CS0_BNDS 0x008000bf 30 #define DDR_CS0_CONFIG 0x80014302 31 #define DDR_TIMING_CFG_0 0x50550004 32 #define DDR_TIMING_CFG_1 0xbcb38c56 33 #define DDR_TIMING_CFG_2 0x0040d120 34 #define DDR_TIMING_CFG_3 0x010e1000 35 #define DDR_TIMING_CFG_4 0x00000001 36 #define DDR_TIMING_CFG_5 0x03401400 37 #define DDR_SDRAM_CFG_2 0x00401010 [all …]
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H A D | ls1021atwr.h | 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 [all …]
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/openbmc/linux/drivers/gpu/drm/imx/dcss/ |
H A D | dcss-drv.c | 40 int err = 0; in dcss_drv_platform_probe() 46 remote = of_graph_get_remote_node(dev->of_node, 0, 0); in dcss_drv_platform_probe() 73 return 0; in dcss_drv_platform_probe() 92 return 0; in dcss_drv_platform_remove() 98 .blkctl_ofs = 0x2F000, 99 .ctxld_ofs = 0x23000, 100 .dtg_ofs = 0x20000, 101 .scaler_ofs = 0x1C000, 102 .ss_ofs = 0x1B000, 103 .dpr_ofs = 0x18000,
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/openbmc/linux/arch/powerpc/boot/dts/fsl/ |
H A D | qoriq-bman1-portals.dtsi | 40 bman-portal@0 { 42 reg = <0x0 0x4000>, <0x100000 0x1000>; 43 interrupts = <105 2 0 0>; 47 reg = <0x4000 0x4000>, <0x101000 0x1000>; 48 interrupts = <107 2 0 0>; 52 reg = <0x8000 0x4000>, <0x102000 0x1000>; 53 interrupts = <109 2 0 0>; 57 reg = <0xc000 0x4000>, <0x103000 0x1000>; 58 interrupts = <111 2 0 0>; 62 reg = <0x10000 0x4000>, <0x104000 0x1000>; [all …]
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H A D | qoriq-qman1-portals.dtsi | 40 qportal0: qman-portal@0 { 42 reg = <0x0 0x4000>, <0x100000 0x1000>; 43 interrupts = <104 2 0 0>; 44 cell-index = <0x0>; 48 reg = <0x4000 0x4000>, <0x101000 0x1000>; 49 interrupts = <106 2 0 0>; 54 reg = <0x8000 0x4000>, <0x102000 0x1000>; 55 interrupts = <108 2 0 0>; 60 reg = <0xc000 0x4000>, <0x103000 0x1000>; 61 interrupts = <110 2 0 0>; [all …]
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H A D | b4si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 71 reg = <0 0 0 0 0>; 72 interrupts = <20 2 0 0>; [all …]
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H A D | p1010si-post.dtsi | 39 interrupts = <16 2 0 0 19 2 0 0>; 42 /* controller at 0x9000 */ 48 bus-range = <0 255>; 50 interrupts = <16 2 0 0>; 52 pcie@0 { 53 reg = <0 0 0 0 0>; 58 interrupts = <16 2 0 0>; 59 interrupt-map-mask = <0xf800 0 0 7>; 61 /* IDSEL 0x0 */ 62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 [all …]
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H A D | t2081si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 67 reg = <0 0 0 0 0>; [all …]
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H A D | t1040si-post.dtsi | 39 alloc-ranges = <0 0 0x10000 0>; 44 alloc-ranges = <0 0 0x10000 0>; 49 alloc-ranges = <0 0 0x10000 0>; 56 interrupts = <25 2 0 0>; 64 bus-range = <0x0 0xff>; 65 interrupts = <20 2 0 0>; 67 pcie@0 { 68 reg = <0 0 0 0 0>; 73 interrupts = <20 2 0 0>; 74 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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H A D | t4240si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 65 pcie@0 { 70 reg = <0 0 0 0 0>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mfd/ |
H A D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$": 53 "^clock-controller@[0-9a-f]+$": 59 "phy@[0-9a-f]+$": 65 "^chipid@[0-9a-f]+$": 84 reg = <0x00100000 0x1c000>; 91 reg = <0x00004080 0x50>; 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
H A D | cpu_sun9i.h | 12 #define REGS_AHB0_BASE 0x01C00000 13 #define REGS_AHB1_BASE 0x00800000 14 #define REGS_AHB2_BASE 0x03000000 15 #define REGS_APB0_BASE 0x06000000 16 #define REGS_APB1_BASE 0x07000000 17 #define REGS_RCPUS_BASE 0x08000000 19 #define SUNXI_SRAM_D_BASE 0x08100000 22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) 23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) 25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) [all …]
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/openbmc/linux/arch/sparc/kernel/ |
H A D | traps_32.c | 47 #define __SAVE __asm__ __volatile__("save %sp, -0x40, %sp\n\t") 53 int count = 0; in die_if_kernel() 81 !(((unsigned long) rw) & 0x7)) { in die_if_kernel() 94 if(type < 0x80) { in do_hw_interrupt() 104 (void __user *)regs->pc, type - 0x80); in do_hw_interrupt() 139 #if 0 in do_memaccess_unaligned() 145 /* FIXME: Should dig out mna address */ (void *)0, in do_memaccess_unaligned() 149 static unsigned long init_fsr = 0x0UL; 151 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, 152 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/can/ |
H A D | fsl,flexcan.yaml | 94 maximum: 0xff 96 maximum: 0x1f 104 0: clock source 0 (oscillator clock) 108 minimum: 0 123 minimum: 0 140 reg = <0x1c000 0x1000>; 141 interrupts = <48 0x2>; 144 fsl,clk-source = /bits/ 8 <0>; 151 reg = <0x02090000 0x4000>; 152 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
H A D | imx-regs.h | 11 #define ROMCP_ARB_BASE_ADDR 0x00000000 12 #define ROMCP_ARB_END_ADDR 0x000FFFFF 15 #define GPU_2D_ARB_BASE_ADDR 0x02200000 16 #define GPU_2D_ARB_END_ADDR 0x02203FFF 17 #define OPENVG_ARB_BASE_ADDR 0x02204000 18 #define OPENVG_ARB_END_ADDR 0x02207FFF 20 #define CAAM_ARB_BASE_ADDR 0x00100000 21 #define CAAM_ARB_END_ADDR 0x00107FFF 22 #define GPU_ARB_BASE_ADDR 0x01800000 23 #define GPU_ARB_END_ADDR 0x01803FFF [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | msm8953-motorola-potter.dts | 18 qcom,msm-id = <293 0>; 19 qcom,board-id = <0x46 0x83a0>; 28 reg = <0 0x90001000 0 (2220 * 1920 * 3)>; 51 pinctrl-0 = <&gpio_key_default>; 62 reg = <0x0 0x84300000 0x0 0x2000000>; 67 reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; 72 reg = <0x0 0xaefd2000 0x0 0x2e000>; 77 reg = <0x0 0xeefe4000 0x0 0x1c000>; 83 reg = <0x0 0xef000000 0x0 0x80000>; 84 console-size = <0x40000>; [all …]
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/openbmc/linux/drivers/gpu/drm/lima/ |
H A D | lima_device.c | 52 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"), 53 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL), 54 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL), 55 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL), 56 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"), 57 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"), 58 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"), 59 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"), 60 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"), 61 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"), [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx27/ |
H A D | imx-regs.h | 65 u32 cs0u; /* Chip Select 0 Upper Register */ 66 u32 cs0l; /* Chip Select 0 Lower Register */ 67 u32 cs0a; /* Chip Select 0 Addition Register */ 94 /* Enhanced SDRAM Control Register 0 */ 96 /* Enhanced SDRAM Configuration Register 0 */ 116 u32 mpctl0; /* MCU PLL Control Register 0 */ 118 u32 spctl0; /* System PLL Control Register 0 */ 121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */ 123 u32 pccr0; /* Peripheral Clock Control Register 0 */ 157 u32 res[0x1f1]; [all …]
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/openbmc/linux/drivers/scsi/qla2xxx/ |
H A D | qla_sup.c | 35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access() 39 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access() 42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access() 60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); in qla2x00_unlock_nvram_access() 98 * Bit 15-0 = write data 107 uint16_t data = 0; in qla2x00_nvram_request() 112 for (cnt = 0; cnt < 11; cnt++) { in qla2x00_nvram_request() 116 qla2x00_nv_write(ha, 0); in qla2x00_nvram_request() 121 for (cnt = 0; cnt < 16; cnt++) { in qla2x00_nvram_request() 194 qla2x00_nv_write(ha, 0); in qla2x00_write_nvram_word() [all …]
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/openbmc/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-sdx65.dtsi | 20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; 25 reg = <0 0>; 33 #clock-cells = <0>; 40 #clock-cells = <0>; 46 #clock-cells = <0>; 52 #size-cells = <0>; 54 cpu0: cpu@0 { 57 reg = <0x0>; 115 reg = <0x8fcad000 0x40000>; 120 reg = <0x8fcfd000 0x1000>; [all …]
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