/openbmc/linux/drivers/media/platform/chips-media/ |
H A D | coda_regs.h | 14 #define CODA_REG_BIT_CODE_RUN 0x000 15 #define CODA_REG_RUN_ENABLE (1 << 0) 16 #define CODA_REG_BIT_CODE_DOWN 0x004 17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16) 18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff) 19 #define CODA_REG_BIT_HOST_IN_REQ 0x008 20 #define CODA_REG_BIT_INT_CLEAR 0x00c 21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1 22 #define CODA_REG_BIT_INT_STATUS 0x010 23 #define CODA_REG_BIT_CODE_RESET 0x014 [all …]
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/openbmc/linux/drivers/clk/hisilicon/ |
H A D | clk-hi3559a.c | 22 #define CRG_BASE_ADDR 0x18020000 62 { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, }, 63 { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, }, 64 { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, }, 65 { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, }, 66 { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, }, 67 { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, }, 68 { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, }, 69 { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, }, 70 { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, }, [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcs-v6.h | 10 #define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc 11 #define QPHY_V6_PCS_RX_SIGDET_LVL 0x188 12 #define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198 13 #define QPHY_V6_PCS_EQ_CONFIG2 0x1e0 14 #define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
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H A D | phy-qcom-qmp-pcs-v5.h | 10 #define QPHY_V5_PCS_SW_RESET 0x000 11 #define QPHY_V5_PCS_PCS_STATUS1 0x014 12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040 13 #define QPHY_V5_PCS_START_CONTROL 0x044 14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc 17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8 18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v6.h | 11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00 12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04 13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10 14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14 15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18 16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c 17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20 18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24 19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28 20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc 20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c [all …]
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H A D | phy-qcom-qmp-qserdes-com-v5.h | 10 #define QSERDES_V5_COM_ATB_SEL1 0x000 11 #define QSERDES_V5_COM_ATB_SEL2 0x004 12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008 13 #define QSERDES_V5_COM_BG_TIMER 0x00c 14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_V5_COM_SSC_PER1 0x01c 18 #define QSERDES_V5_COM_SSC_PER2 0x020 19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v4.h | 10 #define QSERDES_V4_COM_ATB_SEL1 0x000 11 #define QSERDES_V4_COM_ATB_SEL2 0x004 12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008 13 #define QSERDES_V4_COM_BG_TIMER 0x00c 14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_V4_COM_SSC_PER1 0x01c 18 #define QSERDES_V4_COM_SSC_PER2 0x020 19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 [all …]
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H A D | phy-qcom-qmp-pcie-qhp.h | 10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c [all …]
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H A D | phy-qcom-qmp-pcs-v3.h | 10 #define QPHY_V3_PCS_SW_RESET 0x000 11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V3_PCS_START_CONTROL 0x008 13 #define QPHY_V3_PCS_TXMGN_V0 0x00c 14 #define QPHY_V3_PCS_TXMGN_V1 0x010 15 #define QPHY_V3_PCS_TXMGN_V2 0x014 16 #define QPHY_V3_PCS_TXMGN_V3 0x018 17 #define QPHY_V3_PCS_TXMGN_V4 0x01c 18 #define QPHY_V3_PCS_TXMGN_LS 0x020 19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-com.h | 10 #define QSERDES_COM_ATB_SEL1 0x000 11 #define QSERDES_COM_ATB_SEL2 0x004 12 #define QSERDES_COM_FREQ_UPDATE 0x008 13 #define QSERDES_COM_BG_TIMER 0x00c 14 #define QSERDES_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_COM_SSC_PER1 0x01c 18 #define QSERDES_COM_SSC_PER2 0x020 19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024 [all …]
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H A D | phy-qcom-qmp-pcs-v4.h | 10 #define QPHY_V4_PCS_SW_RESET 0x000 11 #define QPHY_V4_PCS_REVISION_ID0 0x004 12 #define QPHY_V4_PCS_REVISION_ID1 0x008 13 #define QPHY_V4_PCS_REVISION_ID2 0x00c 14 #define QPHY_V4_PCS_REVISION_ID3 0x010 15 #define QPHY_V4_PCS_PCS_STATUS1 0x014 16 #define QPHY_V4_PCS_PCS_STATUS2 0x018 17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c 18 #define QPHY_V4_PCS_PCS_STATUS4 0x020 19 #define QPHY_V4_PCS_PCS_STATUS5 0x024 [all …]
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/openbmc/qemu/linux-user/hppa/ |
H A D | vdso-asmoffset.h | 3 #define offsetof_sigcontext_gr 0x4 4 #define offsetof_sigcontext_fr 0x88 5 #define offsetof_sigcontext_iaoq 0x190 6 #define offsetof_sigcontext_sar 0x198
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/openbmc/u-boot/include/ |
H A D | cortina.h | 11 #define VILLA_GLOBAL_CHIP_ID_LSB 0x000 12 #define VILLA_GLOBAL_CHIP_ID_MSB 0x001 13 #define VILLA_GLOBAL_BIST_CONTROL 0x002 14 #define VILLA_GLOBAL_BIST_STATUS 0x003 15 #define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 16 #define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 17 #define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A 18 #define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B 19 #define VILLA_GLOBAL_MSEQCLKCTRL 0x00E 20 #define VILLA_MSEQ_OPTIONS 0x1D0 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | vf610-pinfunc.h | 18 #define ALT0 0x0 19 #define ALT1 0x1 20 #define ALT2 0x2 21 #define ALT3 0x3 22 #define ALT4 0x4 23 #define ALT5 0x5 24 #define ALT6 0x6 25 #define ALT7 0x7 28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/linux/tools/power/cpupower/utils/helpers/ |
H A D | msr.c | 12 #define MSR_IA32_PERF_STATUS 0x198 13 #define MSR_IA32_MISC_ENABLES 0x1a0 14 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1ad 19 * Will return 0 on success and -1 on failure. 33 if (fd < 0) in read_msr() 40 return 0; in read_msr() 49 * Will return 0 on success and -1 on failure. 62 if (fd < 0) in write_msr() 69 return 0; in write_msr()
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/openbmc/linux/tools/power/cpupower/debug/i386/ |
H A D | centrino-decode.c | 9 * USAGE: simply run it to decode the current settings on CPU 0, 26 #define MSR_IA32_PERF_STATUS 0x198 36 *lo = *hi = 0; in rdmsr() 44 if (fd < 0) in rdmsr() 53 *lo = (uint32_t )(val & 0xffffffffull); in rdmsr() 54 *hi = (uint32_t )(val>>32 & 0xffffffffull); in rdmsr() 56 retval = 0; in rdmsr() 68 multiplier = ((msr >> 8) & 0xFF); in decode() 70 mv = (((msr & 0xFF) * 16) + 700); in decode() 72 printf("0x%x means multiplier %d @ %d mV\n", msr, multiplier, mv); in decode() [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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/openbmc/u-boot/include/dt-bindings/pinctrl/ |
H A D | pins-imx8mq.h | 24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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/openbmc/linux/drivers/crypto/caam/ |
H A D | dpseci_cmd.h | 29 #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800) 30 #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809) 31 #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09) 33 #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002) 34 #define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003) 35 #define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004) 36 #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005) 37 #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006) 39 #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194) 40 #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196) [all …]
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/openbmc/linux/drivers/soc/tegra/fuse/ |
H A D | fuse-tegra30.c | 21 #define FUSE_BEGIN 0x100 24 #define FUSE_VENDOR_CODE 0x100 25 #define FUSE_FAB_CODE 0x104 26 #define FUSE_LOT_CODE_0 0x108 27 #define FUSE_LOT_CODE_1 0x10c 28 #define FUSE_WAFER_ID 0x110 29 #define FUSE_X_COORDINATE 0x114 30 #define FUSE_Y_COORDINATE 0x118 32 #define FUSE_HAS_REVISION_INFO BIT(0) 45 return 0; in tegra30_fuse_read_early() [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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