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/openbmc/u-boot/board/imgtec/boston/
H A Dboston-regs.h11 #define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000)
12 #define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000)
17 #define BOSTON_PLAT_CORE_CL (BOSTON_PLAT_BASE + 0x04)
19 #define BOSTON_PLAT_DDR3STAT (BOSTON_PLAT_BASE + 0x14)
22 #define BOSTON_PLAT_DDRCONF0 (BOSTON_PLAT_BASE + 0x38)
23 # define BOSTON_PLAT_DDRCONF0_SIZE (0xf << 0)
/openbmc/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dimg,ascii-lcd.yaml54 reg = <0x17fff000 0x8>;
/openbmc/u-boot/arch/mips/dts/
H A Dimg,boston.dts19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
29 memory@0 {
31 reg = <0x00000000 0x10000000>;
51 reg = <0x10000000 0x2000000>;
60 ranges = <0x02000000 0 0x40000000
61 0x40000000 0 0x40000000>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 1 &pci0_intc 0>,
[all …]
/openbmc/linux/arch/mips/boot/dts/img/
H A Dboston.dts24 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
34 memory@0 {
36 reg = <0x00000000 0x10000000>;
42 reg = <0x10000000 0x2000000>;
51 ranges = <0x02000000 0 0x40000000
52 0x40000000 0 0x40000000>;
54 bus-range = <0x00 0xff>;
56 interrupt-map-mask = <0 0 0 7>;
[all …]
/openbmc/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi6 /memreserve/ 0x00000000 0x0000a800; /* boot code */
7 /memreserve/ 0x0000a800 0x000f5800;
8 /memreserve/ 0x17fff000 0x00001000;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0x0>;
33 reg = <0x1>;
44 reg = <0x0000b000 0x1000>;
48 reg = <0x01b00000 0x400000>;
52 reg = <0x01ffe000 0x4000>;
[all …]
/openbmc/qemu/hw/mips/
H A Dboston.c54 #define FDT_IRQ_TYPE_NONE 0
56 #define FDT_GIC_SHARED 0
99 [BOSTON_LOWDDR] = { 0x0, 0x10000000 },
100 [BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
101 [BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
102 [BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
103 [BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
104 [BOSTON_CM] = { 0x16100000, 0x20000 },
105 [BOSTON_GIC] = { 0x16120000, 0x20000 },
106 [BOSTON_CDMM] = { 0x16140000, 0x8000 },
[all …]