54 #define FDT_IRQ_TYPE_NONE       0
56 #define FDT_GIC_SHARED          0
99     [BOSTON_LOWDDR] =     {        0x0,    0x10000000 },
100     [BOSTON_PCIE0] =      { 0x10000000,     0x2000000 },
101     [BOSTON_PCIE1] =      { 0x12000000,     0x2000000 },
102     [BOSTON_PCIE2] =      { 0x14000000,     0x2000000 },
103     [BOSTON_PCIE2_MMIO] = { 0x16000000,      0x100000 },
104     [BOSTON_CM] =         { 0x16100000,       0x20000 },
105     [BOSTON_GIC] =        { 0x16120000,       0x20000 },
106     [BOSTON_CDMM] =       { 0x16140000,        0x8000 },
107     [BOSTON_CPC] =        { 0x16200000,        0x8000 },
108     [BOSTON_PLATREG] =    { 0x17ffd000,        0x1000 },
109     [BOSTON_UART] =       { 0x17ffe000,          0x20 },
110     [BOSTON_LCD] =        { 0x17fff000,           0x8 },
111     [BOSTON_FLASH] =      { 0x18000000,     0x8000000 },
112     [BOSTON_PCIE1_MMIO] = { 0x20000000,    0x20000000 },
113     [BOSTON_PCIE0_MMIO] = { 0x40000000,    0x40000000 },
114     [BOSTON_HIGHDDR] =    { 0x80000000,           0x0 },
118     PLAT_FPGA_BUILD     = 0x00,
119     PLAT_CORE_CL        = 0x04,
120     PLAT_WRAPPER_CL     = 0x08,
121     PLAT_SYSCLK_STATUS  = 0x0c,
122     PLAT_SOFTRST_CTL    = 0x10,
124     PLAT_DDR3_STATUS    = 0x14,
125 #define PLAT_DDR3_STATUS_LOCKED         (1 << 0)
127     PLAT_PCIE_STATUS    = 0x18,
128 #define PLAT_PCIE_STATUS_PCIE0_LOCKED   (1 << 0)
131     PLAT_FLASH_CTL      = 0x1c,
132     PLAT_SPARE0         = 0x20,
133     PLAT_SPARE1         = 0x24,
134     PLAT_SPARE2         = 0x28,
135     PLAT_SPARE3         = 0x2c,
136     PLAT_MMCM_DIV       = 0x30,
137 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT     0
141     PLAT_BUILD_CFG      = 0x34,
142 #define PLAT_BUILD_CFG_IOCU_EN          (1 << 0)
146     PLAT_DDR_CFG        = 0x38,
147 #define PLAT_DDR_CFG_SIZE               (0xf << 0)
148 #define PLAT_DDR_CFG_MHZ                (0xfff << 4)
149     PLAT_NOC_PCIE0_ADDR = 0x3c,
150     PLAT_NOC_PCIE1_ADDR = 0x40,
151     PLAT_NOC_PCIE2_ADDR = 0x44,
152     PLAT_SYS_CTL        = 0x48,
168     uint64_t val = 0;  in boston_lcd_read()
172         val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;  in boston_lcd_read()
173         val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;  in boston_lcd_read()
174         val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;  in boston_lcd_read()
175         val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;  in boston_lcd_read()
178         val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;  in boston_lcd_read()
179         val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;  in boston_lcd_read()
182         val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;  in boston_lcd_read()
185         val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];  in boston_lcd_read()
199         s->lcd_content[(addr + 7) & 0x7] = val >> 56;  in boston_lcd_write()
200         s->lcd_content[(addr + 6) & 0x7] = val >> 48;  in boston_lcd_write()
201         s->lcd_content[(addr + 5) & 0x7] = val >> 40;  in boston_lcd_write()
202         s->lcd_content[(addr + 4) & 0x7] = val >> 32;  in boston_lcd_write()
205         s->lcd_content[(addr + 3) & 0x7] = val >> 24;  in boston_lcd_write()
206         s->lcd_content[(addr + 2) & 0x7] = val >> 16;  in boston_lcd_write()
209         s->lcd_content[(addr + 1) & 0x7] = val >> 8;  in boston_lcd_write()
212         s->lcd_content[(addr + 0) & 0x7] = val;  in boston_lcd_write()
234         return 0;  in boston_platreg_read()
237     switch (addr & 0xffff) {  in boston_platreg_read()
241         return 0;  in boston_platreg_read()
262         qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",  in boston_platreg_read()
263                       addr & 0xffff);  in boston_platreg_read()
264         return 0;  in boston_platreg_read()
276     switch (addr & 0xffff) {  in boston_platreg_write()
293         qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx  in boston_platreg_write()
294                       " = 0x%" PRIx64 "\n", addr & 0xffff, val);  in boston_platreg_write()
352      * a2/$6 = 0  in type_init()
353      * a3/$7 = 0  in type_init()
356                        true, 0, true, (int32_t)-2,  in type_init()
357                        true, fdt_addr, true, 0, true, 0,  in type_init()
382     cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0])  in boston_fdt_filter()
385     if (err < 0) {  in boston_fdt_filter()
392     qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",  in boston_fdt_filter()
446     cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);  in xilinx_pcie_init()
447     memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);  in xilinx_pcie_init()
450     memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);  in xilinx_pcie_init()
452     qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);  in xilinx_pcie_init()
482     qemu_fdt_setprop_cells(fdt, name, "ranges", 0x02000000, 0, mmio_base,  in fdt_create_pcie()
483                             mmio_base, 0, mmio_size);  in fdt_create_pcie()
484     qemu_fdt_setprop_cells(fdt, name, "bus-range", 0x00, 0xff);  in fdt_create_pcie()
490     qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);  in fdt_create_pcie()
491     qemu_fdt_setprop_cell(fdt, intc_name, "#address-cells", 0);  in fdt_create_pcie()
495     qemu_fdt_setprop_cells(fdt, name, "interrupt-map-mask", 0, 0, 0, 7);  in fdt_create_pcie()
496     for (i = 0; i < FDT_PCI_IRQ_MAP_PINS; i++) {  in fdt_create_pcie()
499         irqmap[0] = cpu_to_be32(0);  in fdt_create_pcie()
500         irqmap[1] = cpu_to_be32(0);  in fdt_create_pcie()
501         irqmap[2] = cpu_to_be32(0);  in fdt_create_pcie()
537     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);  in create_fdt()
538     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);  in create_fdt()
542     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);  in create_fdt()
543     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);  in create_fdt()
545     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {  in create_fdt()
557     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);  in create_fdt()
559     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);  in create_fdt()
560     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);  in create_fdt()
570     fdt_create_pcie(fdt, gic_ph, 0,  in create_fdt()
581     qemu_fdt_setprop(fdt, gic_name, "interrupt-controller", NULL, 0);  in create_fdt()
635     qemu_fdt_setprop_cell(fdt, name, "offset", 0x10);  in create_fdt()
636     qemu_fdt_setprop_cell(fdt, name, "mask", 0x10);  in create_fdt()
645     qemu_fdt_setprop_cell(fdt, name, "reg-shift", 0x2);  in create_fdt()
665     name = g_strdup_printf("/memory@0");  in create_fdt()
712     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);  in boston_mach_init()
719                                         flash, 0);  in boston_mach_init()
723                                         machine->ram, 0);  in boston_mach_init()
727                              machine->ram, 0,  in boston_mach_init()
729     memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);  in boston_mach_init()
731     xilinx_pcie_init(sys_mem, 0,  in boston_mach_init()
750                              get_cps_irq(&s->cps, 0));  in boston_mach_init()
757                           boston_memmap[BOSTON_PLATREG].base, platreg, 0);  in boston_mach_init()
761                              serial_hd(0), DEVICE_NATIVE_ENDIAN);  in boston_mach_init()
764     memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);  in boston_mach_init()
766                                         boston_memmap[BOSTON_LCD].base, lcd, 0);  in boston_mach_init()
774                                            PCI_DEVFN(0, 0), TYPE_ICH9_AHCI);  in boston_mach_init()
782                                       0x1fc00000, 4 * MiB);  in boston_mach_init()
795                            NULL, 0, EM_MIPS, 1, 0);  in boston_mach_init()
797         if (kernel_size > 0) {  in boston_mach_init()
828         gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,  in boston_mach_init()