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/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0 0x0>;
41 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
86 reg = <0x0 0x200>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x300>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]