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/openbmc/linux/drivers/pmdomain/mediatek/
H A Dmt8186-pm-domains.h21 .ctl_offs = 0x308,
22 .pwr_sta_offs = 0x16C,
23 .pwr_sta2nd_offs = 0x170,
31 .ctl_offs = 0x30c,
32 .pwr_sta_offs = 0x16C,
33 .pwr_sta2nd_offs = 0x170,
59 .ctl_offs = 0x310,
60 .pwr_sta_offs = 0x16C,
61 .pwr_sta2nd_offs = 0x170,
69 .ctl_offs = 0x314,
[all …]
H A Dmt8188-pm-domains.h21 .ctl_offs = 0x300,
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
31 .ctl_offs = 0x304,
32 .pwr_sta_offs = 0x174,
33 .pwr_sta2nd_offs = 0x178,
67 .ctl_offs = 0x308,
68 .pwr_sta_offs = 0x174,
69 .pwr_sta2nd_offs = 0x178,
77 .ctl_offs = 0x30C,
[all …]
H A Dmt8195-pm-domains.h21 .ctl_offs = 0x328,
22 .pwr_sta_offs = 0x174,
23 .pwr_sta2nd_offs = 0x178,
40 .ctl_offs = 0x32C,
41 .pwr_sta_offs = 0x174,
42 .pwr_sta2nd_offs = 0x178,
59 .ctl_offs = 0x330,
60 .pwr_sta_offs = 0x174,
61 .pwr_sta2nd_offs = 0x178,
67 .ctl_offs = 0x334,
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_PER1 0x01c
12 #define QSERDES_PLL_SSC_PER2 0x020
13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
18 #define QSERDES_PLL_CLK_ENABLE1 0x040
19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v6.h9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/openbmc/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmmc_host_def.h31 #define T2_BASE 0x48002000
34 unsigned char res1[0x274]; /* 0x000 */
35 unsigned int devconf0; /* 0x274 */
36 unsigned char res2[0x060]; /* 0x278 */
37 unsigned int devconf1; /* 0x2D8 */
38 unsigned char res3[0x16C]; /* 0x2DC */
39 unsigned int ctl_prog_io1; /* 0x448 */
40 unsigned char res4[0x0D4]; /* 0x44C */
41 unsigned int pbias_lite; /* 0x520 */
55 #define PBIASLITEVMODE0 (1 << 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imxrt1170.yaml71 reg = <0x400e8000 0x4000>;
74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dgtbus_sun9i.h15 u32 mst_cfg[36]; /* 0x000 */
16 u8 reserved1[0x70]; /* 0x090 */
17 u32 bw_wdw_cfg; /* 0x100 */
18 u32 mst_read_prio_cfg[2]; /* 0x104 */
19 u32 lvl2_mst_cfg; /* 0x10c */
20 u32 sw_clk_on; /* 0x110 */
21 u32 sw_clk_off; /* 0x114 */
22 u32 pmu_mst_en; /* 0x118 */
23 u32 pmu_cfg; /* 0x11c */
24 u32 pmu_cnt[19]; /* 0x120 */
[all …]
/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hi3559a.c22 #define CRG_BASE_ADDR 0x18020000
62 { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
63 { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
64 { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
65 { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
66 { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
67 { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
68 { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
69 { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
70 { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpins-imx8mq.h24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
[all …]
/openbmc/linux/arch/mips/include/asm/mach-lantiq/xway/
H A Dlantiq_soc.h15 #define SOC_ID_DANUBE1 0x129
16 #define SOC_ID_DANUBE2 0x12B
17 #define SOC_ID_TWINPASS 0x12D
18 #define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
19 #define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
20 #define SOC_ID_ARX188 0x16C
21 #define SOC_ID_ARX168_1 0x16D
22 #define SOC_ID_ARX168_2 0x16E
23 #define SOC_ID_ARX182 0x16F
24 #define SOC_ID_GRX188 0x170
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h10 unsigned int pid; /* 0x00 */
11 unsigned char rsvd0[224]; /* 0x04 */
12 unsigned int rstype; /* 0xe4 */
13 unsigned char rsvd1[24]; /* 0xe8 */
14 unsigned int pllctl; /* 0x100 */
15 unsigned char rsvd2[4]; /* 0x104 */
16 unsigned int secctl; /* 0x108 */
17 unsigned int rv; /* 0x10c */
18 unsigned int pllm; /* 0x110 */
19 unsigned int prediv; /* 0x114 */
[all …]

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