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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml79 pinctrl-0:
98 minimum: 0
99 maximum: 0xffffffff
106 The value is an integer from 0 to 31.
107 minimum: 0
115 The value is an integer from 0 to 31.
116 minimum: 0
130 pad macro, there are 32 stages from 0 to 31.
135 minimum: 0
142 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173-elm.dtsi21 reg = <0 0x40000000 0 0x80000000>;
26 pwms = <&pwm0 0 1000000>;
31 pinctrl-0 = <&panel_backlight_en_pins>;
44 pinctrl-0 = <&bl_fixed_pins>;
54 pinctrl-0 = <&gpio_keys_pins>;
103 pinctrl-0 = <&panel_fixed_pins>;
116 pinctrl-0 = <&ps8640_fixed_pins>;
126 pinctrl-0 = <&sdio_fixed_3v3_pins>;
134 pinctrl-0 = <&aud_i2s2>;
237 mediatek,ibias = <0xc>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_2_0_offset.h26 // base address: 0x0
27 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
28 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
29 …BIF_CFG_DEV0_RC_COMMAND 0x0004
30 …BIF_CFG_DEV0_RC_STATUS 0x0006
31 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
32 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
33 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
34 …BIF_CFG_DEV0_RC_BASE_CLASS 0x000b
35 …BIF_CFG_DEV0_RC_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_7_0_offset.h29 // base address: 0x0
30 …NBCFG_SCRATCH_4 0x0078
34 // base address: 0x0
35 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
36 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
37 …BIF_CFG_DEV0_RC_COMMAND 0x0004
38 …BIF_CFG_DEV0_RC_STATUS 0x0006
39 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
40 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
41 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
[all …]