/openbmc/linux/drivers/clk/visconti/ |
H A D | clkc-tmpv770x.c | 35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, }, 37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, }, 39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, }, 42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, }, 43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, }, 44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, }, 51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200, 55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20, 59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10, 63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4, [all …]
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/openbmc/linux/drivers/clk/renesas/ |
H A D | r8a774b1-cpg-mssr.c | 97 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), 98 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), 99 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), 100 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), 101 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), 102 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), 103 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), 104 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), 113 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 114 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), [all …]
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H A D | r8a774a1-cpg-mssr.c | 78 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 100 DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), 116 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a774e1-cpg-mssr.c | 78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 100 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074), 101 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078), 102 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268), 103 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c), 104 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074), 105 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078), 106 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268), 107 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c), 117 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a77965-cpg-mssr.c | 101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074), 102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078), 103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268), 104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c), 105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074), 106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078), 107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268), 108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c), 118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), [all …]
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H A D | r8a7796-cpg-mssr.c | 83 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 106 DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074), 107 DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078), 108 DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268), 109 DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c), 110 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074), 111 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078), 112 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), 113 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), 123 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a7795-cpg-mssr.c | 81 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), 104 DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074), 105 DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078), 106 DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268), 107 DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c), 108 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074), 109 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078), 110 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), 111 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), 121 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), [all …]
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H A D | r8a779a0-cpg-mssr.c | 73 DEF_PLL(".pll20", CLK_PLL20, 0x0834), 74 DEF_PLL(".pll21", CLK_PLL21, 0x0838), 75 DEF_PLL(".pll30", CLK_PLL30, 0x083c), 76 DEF_PLL(".pll31", CLK_PLL31, 0x0840), 94 DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0), 119 DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), 120 DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), 126 DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), 127 DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), 128 DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), [all …]
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/openbmc/u-boot/drivers/clk/renesas/ |
H A D | r8a7795-cpg-mssr.c | 96 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), 97 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), 98 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), 99 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), 101 DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), 114 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), 275 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 276 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 277 * 0 0 1 0 Prohibited setting 278 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 [all …]
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H A D | r8a7796-cpg-mssr.c | 96 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), 97 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), 98 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), 99 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), 101 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238), 248 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 249 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 250 * 0 0 1 0 Prohibited setting 251 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 252 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/ |
H A D | sitronix,st7735r.yaml | 24 Adafruit 1.8" 160x128 Color TFT LCD (Product ID 358 or 618) 30 Okaya 1.44" 128x128 Color TFT LCD (E.g. Renesas YRSK-LCD-PMOD) 64 #size-cells = <0>; 66 display@0{ 68 reg = <0>;
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/openbmc/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-audio.c | 60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq() 63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq() 65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq() 66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq() 67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq() 69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq() 70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq() 71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq() 74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq() [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcie-qhp.h | 10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11 #define QSERDES_V4_TX_BIST_INVERT 0x004 12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 19 #define QSERDES_V4_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 12 #define QSERDES_V5_TX_BIST_INVERT 0x004 13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c 15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014 17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c 19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 20 #define QSERDES_V5_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-ln-shrd-v6.h | 9 #define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0 10 #define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0 11 #define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4 12 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4 13 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8 14 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4 15 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8 16 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc 17 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0 18 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4 [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 217 .set_ofs = 0x120, 218 .clr_ofs = 0x120, 219 .sta_ofs = 0x120, 223 .set_ofs = 0x128, 224 .clr_ofs = 0x128, 225 .sta_ofs = 0x128, 229 .set_ofs = 0x8, 230 .clr_ofs = 0x10, 231 .sta_ofs = 0x18, 235 .set_ofs = 0xC, [all …]
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H A D | clk-mt6795-topckgen.c | 17 * So we model these clocks' rate as 0, to denote it's not an actual rate. 19 #define DUMMY_RATE 0 23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \ 24 _gate, 0, -1, _flags) 362 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0), 363 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0), 364 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0), 365 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0), 370 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0), 371 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0), [all …]
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H A D | clk-mt8173-topckgen.c | 18 * So we model these clocks' rate as 0, to denote it's not an actual rate. 20 #define DUMMY_RATE 0 24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \ 25 _gate, 0, -1, _flags) 437 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0), 438 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0), 439 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0), 440 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0), 445 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0), 446 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0), [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | am335x-draco.dts | 45 reg = <0x4b000000 1000000>; 53 pinctrl-0 = <&gpio_mux_pins>; 57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */ 58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */ 59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */ 60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */ 61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */ 67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/ 68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | berlin-usb-phy.txt | 6 - #phys-cells: should be 0 13 reg = <0xf774000 0x128>; 14 #phy-cells = <0>; 15 resets = <&chip 0x104 14>;
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/openbmc/linux/arch/x86/crypto/ |
H A D | crc32-pclmul_asm.S | 7 * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE) 24 * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4 25 * #define CONSTANT_R1 0x154442bd4LL 27 * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596 28 * #define CONSTANT_R2 0x1c6e41596LL 31 .octa 0x00000001c6e415960000000154442bd4 33 * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0 34 * #define CONSTANT_R3 0x1751997d0LL 36 * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e 37 * #define CONSTANT_R4 0x0ccaa009eLL [all …]
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/openbmc/u-boot/arch/arc/cpu/arcv1/ |
H A D | ivt.S | 10 j _start /* 0 - 0x000 */ 11 j memory_error /* 1 - 0x008 */ 12 j instruction_error /* 2 - 0x010 */ 16 j interrupt_handler /* 3:31 - 0x018:0xF8 */ 19 j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ 20 j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ 21 j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ 22 j EV_TLBProtV /* 0x118, Protection Violation (0x23) 24 j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ 25 j EV_Trap /* 0x128, Trap exception (0x25) */ [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-stv0991/ |
H A D | stv0991_gpt.h | 19 u32 reserved_2[3]; /* offset 0x18--0x20*/ 29 #define GPT_CR1_CEN 0x0001 33 #define GPT_PRESCALER_128 0x128 36 #define GPT_FREE_RUNNING 0xFFFF
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/openbmc/linux/drivers/tty/serial/8250/ |
H A D | 8250_boca.c | 13 SERIAL8250_PORT(0x100, 12), 14 SERIAL8250_PORT(0x108, 12), 15 SERIAL8250_PORT(0x110, 12), 16 SERIAL8250_PORT(0x118, 12), 17 SERIAL8250_PORT(0x120, 12), 18 SERIAL8250_PORT(0x128, 12), 19 SERIAL8250_PORT(0x130, 12), 20 SERIAL8250_PORT(0x138, 12), 21 SERIAL8250_PORT(0x140, 12), 22 SERIAL8250_PORT(0x148, 12), [all …]
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