117bcc803SYoshihiro Shimoda // SPDX-License-Identifier: GPL-2.0
217bcc803SYoshihiro Shimoda /*
317bcc803SYoshihiro Shimoda * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
417bcc803SYoshihiro Shimoda *
517bcc803SYoshihiro Shimoda * Copyright (C) 2020 Renesas Electronics Corp.
617bcc803SYoshihiro Shimoda *
717bcc803SYoshihiro Shimoda * Based on r8a7795-cpg-mssr.c
817bcc803SYoshihiro Shimoda *
917bcc803SYoshihiro Shimoda * Copyright (C) 2015 Glider bvba
1017bcc803SYoshihiro Shimoda * Copyright (C) 2015 Renesas Electronics Corp.
1117bcc803SYoshihiro Shimoda */
1217bcc803SYoshihiro Shimoda
1317bcc803SYoshihiro Shimoda #include <linux/bitfield.h>
1417bcc803SYoshihiro Shimoda #include <linux/clk.h>
1517bcc803SYoshihiro Shimoda #include <linux/clk-provider.h>
1617bcc803SYoshihiro Shimoda #include <linux/device.h>
1717bcc803SYoshihiro Shimoda #include <linux/err.h>
1817bcc803SYoshihiro Shimoda #include <linux/init.h>
1917bcc803SYoshihiro Shimoda #include <linux/kernel.h>
2017bcc803SYoshihiro Shimoda #include <linux/soc/renesas/rcar-rst.h>
2117bcc803SYoshihiro Shimoda
2217bcc803SYoshihiro Shimoda #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
2317bcc803SYoshihiro Shimoda
2417bcc803SYoshihiro Shimoda #include "renesas-cpg-mssr.h"
25470e3f0dSYoshihiro Shimoda #include "rcar-gen4-cpg.h"
2617bcc803SYoshihiro Shimoda
2717bcc803SYoshihiro Shimoda enum clk_ids {
2817bcc803SYoshihiro Shimoda /* Core Clock Outputs exported to DT */
2917bcc803SYoshihiro Shimoda LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
3017bcc803SYoshihiro Shimoda
3117bcc803SYoshihiro Shimoda /* External Input Clocks */
3217bcc803SYoshihiro Shimoda CLK_EXTAL,
3317bcc803SYoshihiro Shimoda CLK_EXTALR,
3417bcc803SYoshihiro Shimoda
3517bcc803SYoshihiro Shimoda /* Internal Core Clocks */
3617bcc803SYoshihiro Shimoda CLK_MAIN,
3717bcc803SYoshihiro Shimoda CLK_PLL1,
3817bcc803SYoshihiro Shimoda CLK_PLL20,
3917bcc803SYoshihiro Shimoda CLK_PLL21,
4017bcc803SYoshihiro Shimoda CLK_PLL30,
4117bcc803SYoshihiro Shimoda CLK_PLL31,
4217bcc803SYoshihiro Shimoda CLK_PLL5,
4317bcc803SYoshihiro Shimoda CLK_PLL1_DIV2,
4417bcc803SYoshihiro Shimoda CLK_PLL20_DIV2,
4517bcc803SYoshihiro Shimoda CLK_PLL21_DIV2,
4617bcc803SYoshihiro Shimoda CLK_PLL30_DIV2,
4717bcc803SYoshihiro Shimoda CLK_PLL31_DIV2,
4817bcc803SYoshihiro Shimoda CLK_PLL5_DIV2,
4917bcc803SYoshihiro Shimoda CLK_PLL5_DIV4,
5017bcc803SYoshihiro Shimoda CLK_S1,
5117bcc803SYoshihiro Shimoda CLK_S3,
5217bcc803SYoshihiro Shimoda CLK_SDSRC,
5317bcc803SYoshihiro Shimoda CLK_RPCSRC,
5417bcc803SYoshihiro Shimoda CLK_OCO,
5517bcc803SYoshihiro Shimoda
5617bcc803SYoshihiro Shimoda /* Module Clocks */
5717bcc803SYoshihiro Shimoda MOD_CLK_BASE
5817bcc803SYoshihiro Shimoda };
5917bcc803SYoshihiro Shimoda
6017bcc803SYoshihiro Shimoda #define DEF_PLL(_name, _id, _offset) \
61470e3f0dSYoshihiro Shimoda DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
6217bcc803SYoshihiro Shimoda .offset = _offset)
6317bcc803SYoshihiro Shimoda
6417bcc803SYoshihiro Shimoda static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
6517bcc803SYoshihiro Shimoda /* External Clock Inputs */
6617bcc803SYoshihiro Shimoda DEF_INPUT("extal", CLK_EXTAL),
6717bcc803SYoshihiro Shimoda DEF_INPUT("extalr", CLK_EXTALR),
6817bcc803SYoshihiro Shimoda
6917bcc803SYoshihiro Shimoda /* Internal Core Clocks */
70470e3f0dSYoshihiro Shimoda DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
71470e3f0dSYoshihiro Shimoda DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
72470e3f0dSYoshihiro Shimoda DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
7317bcc803SYoshihiro Shimoda DEF_PLL(".pll20", CLK_PLL20, 0x0834),
7417bcc803SYoshihiro Shimoda DEF_PLL(".pll21", CLK_PLL21, 0x0838),
7517bcc803SYoshihiro Shimoda DEF_PLL(".pll30", CLK_PLL30, 0x083c),
7617bcc803SYoshihiro Shimoda DEF_PLL(".pll31", CLK_PLL31, 0x0840),
7717bcc803SYoshihiro Shimoda
7817bcc803SYoshihiro Shimoda DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
7917bcc803SYoshihiro Shimoda DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
8017bcc803SYoshihiro Shimoda DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
8117bcc803SYoshihiro Shimoda DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
8217bcc803SYoshihiro Shimoda DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
8317bcc803SYoshihiro Shimoda DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
8417bcc803SYoshihiro Shimoda DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
8517bcc803SYoshihiro Shimoda DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
8617bcc803SYoshihiro Shimoda DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
8779250172SWolfram Sang DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
88880c3fa3SGeert Uytterhoeven
8917bcc803SYoshihiro Shimoda DEF_RATE(".oco", CLK_OCO, 32768),
90880c3fa3SGeert Uytterhoeven
91470e3f0dSYoshihiro Shimoda DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
9217bcc803SYoshihiro Shimoda
9317bcc803SYoshihiro Shimoda /* Core Clock Outputs */
94470e3f0dSYoshihiro Shimoda DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
95470e3f0dSYoshihiro Shimoda DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
9617bcc803SYoshihiro Shimoda DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
9717bcc803SYoshihiro Shimoda DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
9817bcc803SYoshihiro Shimoda DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
9917bcc803SYoshihiro Shimoda DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
10017bcc803SYoshihiro Shimoda DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
10117bcc803SYoshihiro Shimoda DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
10217bcc803SYoshihiro Shimoda DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
10317bcc803SYoshihiro Shimoda DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
10417bcc803SYoshihiro Shimoda DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
10517bcc803SYoshihiro Shimoda DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
10617bcc803SYoshihiro Shimoda DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
10717bcc803SYoshihiro Shimoda DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
10817bcc803SYoshihiro Shimoda DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
10917bcc803SYoshihiro Shimoda DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
11017bcc803SYoshihiro Shimoda DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
11117bcc803SYoshihiro Shimoda DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
11217bcc803SYoshihiro Shimoda DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
11317bcc803SYoshihiro Shimoda DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
11417bcc803SYoshihiro Shimoda DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
11580d3e07eSGeert Uytterhoeven DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
116f08b0d84SGeert Uytterhoeven DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
117c52f4f83SWolfram Sang DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
11817bcc803SYoshihiro Shimoda
119db7076d5SWolfram Sang DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
120470e3f0dSYoshihiro Shimoda DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
12179250172SWolfram Sang
122880c3fa3SGeert Uytterhoeven DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
123880c3fa3SGeert Uytterhoeven DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
124880c3fa3SGeert Uytterhoeven R8A779A0_CLK_RPC),
125880c3fa3SGeert Uytterhoeven
12617bcc803SYoshihiro Shimoda DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
12717bcc803SYoshihiro Shimoda DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
12817bcc803SYoshihiro Shimoda DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
129c346ff5cSKieran Bingham DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
13017bcc803SYoshihiro Shimoda
131470e3f0dSYoshihiro Shimoda DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
132470e3f0dSYoshihiro Shimoda DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
13317bcc803SYoshihiro Shimoda };
13417bcc803SYoshihiro Shimoda
13517bcc803SYoshihiro Shimoda static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
136c5e91ba2SWolfram Sang DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
137c5e91ba2SWolfram Sang DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
138c5e91ba2SWolfram Sang DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
139c5e91ba2SWolfram Sang DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
140c5e91ba2SWolfram Sang DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
141c5e91ba2SWolfram Sang DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
1426c745560SGeert Uytterhoeven DEF_MOD("canfd0", 328, R8A779A0_CLK_S3D2),
14323378e70SJacopo Mondi DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
14423378e70SJacopo Mondi DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
14523378e70SJacopo Mondi DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
14623378e70SJacopo Mondi DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
147417ed58dSKieran Bingham DEF_MOD("du", 411, R8A779A0_CLK_S3D1),
148c346ff5cSKieran Bingham DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI),
149c346ff5cSKieran Bingham DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI),
1500177b509SKieran Bingham DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1),
1510177b509SKieran Bingham DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1),
1522e16d0dfSWolfram Sang DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),
1532e16d0dfSWolfram Sang DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2),
1542e16d0dfSWolfram Sang DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2),
1552e16d0dfSWolfram Sang DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2),
1566893a772SWolfram Sang DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4),
1576893a772SWolfram Sang DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4),
1586893a772SWolfram Sang DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4),
1596893a772SWolfram Sang DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4),
1606893a772SWolfram Sang DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
1616893a772SWolfram Sang DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
1626893a772SWolfram Sang DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
16316927401SNiklas Söderlund DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
16416927401SNiklas Söderlund DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
16516927401SNiklas Söderlund DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
16616927401SNiklas Söderlund DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
167010ce438SGeert Uytterhoeven DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
168010ce438SGeert Uytterhoeven DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
169010ce438SGeert Uytterhoeven DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),
170010ce438SGeert Uytterhoeven DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
171010ce438SGeert Uytterhoeven DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
172010ce438SGeert Uytterhoeven DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
1737f91fe3aSWolfram Sang DEF_MOD("pwm0", 628, R8A779A0_CLK_S1D8),
17427c9d763SWolfram Sang DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
17517bcc803SYoshihiro Shimoda DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
17617bcc803SYoshihiro Shimoda DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
17717bcc803SYoshihiro Shimoda DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
17817bcc803SYoshihiro Shimoda DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
17979250172SWolfram Sang DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
180c9baa3bbSKuninori Morimoto DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2),
181c9baa3bbSKuninori Morimoto DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2),
182c52f4f83SWolfram Sang DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
183c52f4f83SWolfram Sang DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
184c52f4f83SWolfram Sang DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
185c52f4f83SWolfram Sang DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4),
186c52f4f83SWolfram Sang DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4),
1873ae4087bSWolfram Sang DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8),
188874d4eeeSJacopo Mondi DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
189874d4eeeSJacopo Mondi DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
190874d4eeeSJacopo Mondi DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
191874d4eeeSJacopo Mondi DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1),
192874d4eeeSJacopo Mondi DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1),
193874d4eeeSJacopo Mondi DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1),
194874d4eeeSJacopo Mondi DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1),
195874d4eeeSJacopo Mondi DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1),
196874d4eeeSJacopo Mondi DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1),
197874d4eeeSJacopo Mondi DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1),
198874d4eeeSJacopo Mondi DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1),
199874d4eeeSJacopo Mondi DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1),
200874d4eeeSJacopo Mondi DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1),
201874d4eeeSJacopo Mondi DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1),
202874d4eeeSJacopo Mondi DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1),
203874d4eeeSJacopo Mondi DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1),
204874d4eeeSJacopo Mondi DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1),
205874d4eeeSJacopo Mondi DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1),
206874d4eeeSJacopo Mondi DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1),
207874d4eeeSJacopo Mondi DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1),
208874d4eeeSJacopo Mondi DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1),
209874d4eeeSJacopo Mondi DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1),
210874d4eeeSJacopo Mondi DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1),
211874d4eeeSJacopo Mondi DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1),
212874d4eeeSJacopo Mondi DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1),
213874d4eeeSJacopo Mondi DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1),
214874d4eeeSJacopo Mondi DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1),
215874d4eeeSJacopo Mondi DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1),
216874d4eeeSJacopo Mondi DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1),
217874d4eeeSJacopo Mondi DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1),
218874d4eeeSJacopo Mondi DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1),
219874d4eeeSJacopo Mondi DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1),
220ed447e7dSKieran Bingham DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1),
221ed447e7dSKieran Bingham DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
222ab2ccacdSWolfram Sang DEF_MOD("rwdt", 907, R8A779A0_CLK_R),
2230eedab65SWolfram Sang DEF_MOD("cmt0", 910, R8A779A0_CLK_R),
2240eedab65SWolfram Sang DEF_MOD("cmt1", 911, R8A779A0_CLK_R),
2250eedab65SWolfram Sang DEF_MOD("cmt2", 912, R8A779A0_CLK_R),
2260eedab65SWolfram Sang DEF_MOD("cmt3", 913, R8A779A0_CLK_R),
227f08b0d84SGeert Uytterhoeven DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
228f08b0d84SGeert Uytterhoeven DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
229f08b0d84SGeert Uytterhoeven DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
230f08b0d84SGeert Uytterhoeven DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
231c66424eaSNiklas Söderlund DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK),
23257be2dc8SKieran Bingham DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
23357be2dc8SKieran Bingham DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
23457be2dc8SKieran Bingham DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
23557be2dc8SKieran Bingham DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
23617bcc803SYoshihiro Shimoda };
23717bcc803SYoshihiro Shimoda
238ab2ccacdSWolfram Sang static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
239ab2ccacdSWolfram Sang MOD_CLK_ID(907), /* RWDT */
240ab2ccacdSWolfram Sang };
241ab2ccacdSWolfram Sang
24217bcc803SYoshihiro Shimoda /*
24317bcc803SYoshihiro Shimoda * CPG Clock Data
24417bcc803SYoshihiro Shimoda */
24517bcc803SYoshihiro Shimoda /*
24617bcc803SYoshihiro Shimoda * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
24717bcc803SYoshihiro Shimoda * 14 13 (MHz) 21 31
2487f906eaaSYoshihiro Shimoda * ----------------------------------------------------------------
24917bcc803SYoshihiro Shimoda * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
25017bcc803SYoshihiro Shimoda * 0 1 20 x 1 x106 x180 x106 x120 x160 /19
25117bcc803SYoshihiro Shimoda * 1 0 Prohibited setting
25217bcc803SYoshihiro Shimoda * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32
25317bcc803SYoshihiro Shimoda */
25417bcc803SYoshihiro Shimoda #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
25517bcc803SYoshihiro Shimoda (((md) & BIT(13)) >> 13))
256470e3f0dSYoshihiro Shimoda static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
2577f906eaaSYoshihiro Shimoda /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
2587f906eaaSYoshihiro Shimoda { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
2597f906eaaSYoshihiro Shimoda { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
2607f906eaaSYoshihiro Shimoda { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
2617f906eaaSYoshihiro Shimoda { 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
26217bcc803SYoshihiro Shimoda };
26317bcc803SYoshihiro Shimoda
264470e3f0dSYoshihiro Shimoda
r8a779a0_cpg_mssr_init(struct device * dev)26517bcc803SYoshihiro Shimoda static int __init r8a779a0_cpg_mssr_init(struct device *dev)
26617bcc803SYoshihiro Shimoda {
267470e3f0dSYoshihiro Shimoda const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
268470e3f0dSYoshihiro Shimoda u32 cpg_mode;
26917bcc803SYoshihiro Shimoda int error;
27017bcc803SYoshihiro Shimoda
27117bcc803SYoshihiro Shimoda error = rcar_rst_read_mode_pins(&cpg_mode);
27217bcc803SYoshihiro Shimoda if (error)
27317bcc803SYoshihiro Shimoda return error;
27417bcc803SYoshihiro Shimoda
27517bcc803SYoshihiro Shimoda cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
27617bcc803SYoshihiro Shimoda
277470e3f0dSYoshihiro Shimoda return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
27817bcc803SYoshihiro Shimoda }
27917bcc803SYoshihiro Shimoda
28017bcc803SYoshihiro Shimoda const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
28117bcc803SYoshihiro Shimoda /* Core Clocks */
28217bcc803SYoshihiro Shimoda .core_clks = r8a779a0_core_clks,
28317bcc803SYoshihiro Shimoda .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
28417bcc803SYoshihiro Shimoda .last_dt_core_clk = LAST_DT_CORE_CLK,
28517bcc803SYoshihiro Shimoda .num_total_core_clks = MOD_CLK_BASE,
28617bcc803SYoshihiro Shimoda
28717bcc803SYoshihiro Shimoda /* Module Clocks */
28817bcc803SYoshihiro Shimoda .mod_clks = r8a779a0_mod_clks,
28917bcc803SYoshihiro Shimoda .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
29017bcc803SYoshihiro Shimoda .num_hw_mod_clks = 15 * 32,
29117bcc803SYoshihiro Shimoda
292ab2ccacdSWolfram Sang /* Critical Module Clocks */
293ab2ccacdSWolfram Sang .crit_mod_clks = r8a779a0_crit_mod_clks,
294ab2ccacdSWolfram Sang .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks),
295ab2ccacdSWolfram Sang
29617bcc803SYoshihiro Shimoda /* Callbacks */
29717bcc803SYoshihiro Shimoda .init = r8a779a0_cpg_mssr_init,
298470e3f0dSYoshihiro Shimoda .cpg_clk_register = rcar_gen4_cpg_clk_register,
29917bcc803SYoshihiro Shimoda
300470e3f0dSYoshihiro Shimoda .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
30117bcc803SYoshihiro Shimoda };
302