/openbmc/linux/Documentation/devicetree/bindings/cpufreq/ |
H A D | apple,cluster-cpufreq.yaml | 35 const: 0 51 #size-cells = <0>; 53 cpu@0 { 56 reg = <0x0 0x0>; 64 reg = <0x0 0x10100>; 70 ecluster_opp: opp-table-0 { 108 reg = <0x2 0x10e20000 0 0x1000>; 109 #performance-domain-cells = <0>; 114 reg = <0x2 0x11e20000 0 0x1000>; 115 #performance-domain-cells = <0>;
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/openbmc/linux/arch/arm64/boot/dts/apple/ |
H A D | t600x-dieX.dtsi | 11 reg = <0x2 0x10e20000 0 0x1000>; 12 #performance-domain-cells = <0>; 17 reg = <0x2 0x11e20000 0 0x1000>; 18 #performance-domain-cells = <0>; 23 reg = <0x2 0x12e20000 0 0x1000>; 24 #performance-domain-cells = <0>; 31 reg = <0x2 0x8e080000 0 0x4000>; 38 reg = <0x2 0x8e580000 0 0xc000>; 45 reg = <0x2 0x8e680000 0 0xc000>; 50 reg = <0x2 0x921f0000 0x0 0x4000>; [all …]
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H A D | t8103.dtsi | 23 #size-cells = <0>; 57 cpu_e0: cpu@0 { 60 reg = <0x0 0x0>; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 67 i-cache-size = <0x20000>; 68 d-cache-size = <0x10000>; 74 reg = <0x0 0x1>; 76 cpu-release-addr = <0 0>; /* To be filled by loader */ 81 i-cache-size = <0x20000>; 82 d-cache-size = <0x10000>; [all …]
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H A D | t8112.dtsi | 24 #size-cells = <0>; 58 cpu_e0: cpu@0 { 61 reg = <0x0 0x0>; 63 cpu-release-addr = <0 0>; /* To be filled by loader */ 68 i-cache-size = <0x20000>; 69 d-cache-size = <0x10000>; 75 reg = <0x0 0x1>; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 82 i-cache-size = <0x20000>; 83 d-cache-size = <0x10000>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | mediatek,mt8192-pinctrl.yaml | 149 reg = <0x10005000 0x1000>, 150 <0x11c20000 0x1000>, 151 <0x11d10000 0x1000>, 152 <0x11d30000 0x1000>, 153 <0x11d40000 0x1000>, 154 <0x11e20000 0x1000>, 155 <0x11e70000 0x1000>, 156 <0x11ea0000 0x1000>, 157 <0x11f20000 0x1000>, 158 <0x11f30000 0x1000>, [all …]
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H A D | mediatek,mt6779-pinctrl.yaml | 114 '-[0-9]*$': 158 enum: [0, 1] 165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 170 enum: [0, 1, 2, 3] 177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 182 enum: [0, 1, 2, 3] [all …]
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H A D | mediatek,mt8188-pinctrl.yaml | 188 reg = <0x10005000 0x1000>, 189 <0x11c00000 0x1000>, 190 <0x11e10000 0x1000>, 191 <0x11e20000 0x1000>, 192 <0x11ea0000 0x1000>, 193 <0x1000b000 0x1000>; 199 gpio-ranges = <&pio 0 0 176>; 201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
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H A D | mediatek,mt8195-pinctrl.yaml | 240 reg = <0x10005000 0x1000>, 241 <0x11d10000 0x1000>, 242 <0x11d30000 0x1000>, 243 <0x11d40000 0x1000>, 244 <0x11e20000 0x1000>, 245 <0x11eb0000 0x1000>, 246 <0x11f40000 0x1000>, 247 <0x1000b000 0x1000>; 253 gpio-ranges = <&pio 0 0 144>; 255 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
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H A D | mediatek,mt7981-pinctrl.yaml | 85 "wa_aice1" "wa_aice" 0, 1 86 "wa_aice2" "wa_aice" 0, 1 87 "wm_uart_0" "uart" 0, 1 88 "dfd" "dfd" 0, 1, 4, 5 388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 396 enum: [0, 1, 2, 3] 400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' [all …]
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H A D | mediatek,mt7986-pinctrl.yaml | 86 "watchdog" "watchdog" 0 334 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 339 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 342 enum: [0, 1, 2, 3] 346 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 351 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. [all …]
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/openbmc/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt6779.dtsi | 26 #size-cells = <0>; 28 cpu0: cpu@0 { 32 reg = <0x000>; 39 reg = <0x100>; 46 reg = <0x200>; 53 reg = <0x300>; 60 reg = <0x400>; 67 reg = <0x500>; 74 reg = <0x600>; 81 reg = <0x700>; [all …]
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H A D | mt7986a.dtsi | 21 #size-cells = <0>; 22 cpu0: cpu@0 { 24 reg = <0x0>; 32 reg = <0x1>; 40 reg = <0x2>; 48 reg = <0x3>; 58 #clock-cells = <0>; 73 reg = <0 0x43000000 0 0x30000>; 79 reg = <0 0x4fc00000 0 0x00100000>; 83 reg = <0 0x4fd00000 0 0x40000>; [all …]
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H A D | mt8192.dtsi | 34 #clock-cells = <0>; 43 #clock-cells = <0>; 50 #clock-cells = <0>; 57 #size-cells = <0>; 59 cpu0: cpu@0 { 62 reg = <0x000>; 73 performance-domains = <&performance 0>; 80 reg = <0x100>; 91 performance-domains = <&performance 0>; 98 reg = <0x200>; [all …]
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H A D | mt8195.dtsi | 51 #size-cells = <0>; 53 cpu0: cpu@0 { 56 reg = <0x000>; 58 performance-domains = <&performance 0>; 75 reg = <0x100>; 77 performance-domains = <&performance 0>; 94 reg = <0x200>; 96 performance-domains = <&performance 0>; 113 reg = <0x300>; 115 performance-domains = <&performance 0>; [all …]
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/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos3250.dtsi | 199 #size-cells = <0>; 212 cpu0: cpu@0 { 215 reg = <0>; 259 xusbxti: clock-0 { 261 clock-frequency = <0>; 262 #clock-cells = <0>; 268 clock-frequency = <0>; 269 #clock-cells = <0>; 275 clock-frequency = <0>; 276 #clock-cells = <0>; [all …]
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H A D | exynos4.dtsi | 68 reg = <0x03810000 0x0c>; 79 reg = <0x03830000 0x100>; 88 samsung,idma-addr = <0x03000000>; 95 reg = <0x10000000 0x100>; 100 reg = <0x10500000 0x2000>; 105 reg = <0x12570000 0x14>; 110 reg = <0x10023c40 0x20>; 111 #power-domain-cells = <0>; 117 reg = <0x10023c60 0x20>; 118 #power-domain-cells = <0>; [all …]
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/openbmc/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt7986.c | 11 #define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) 17 _x_bits, 32, 0) 23 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000, 24 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000, 76 PIN_FIELD(0, 100, 0x300, 0x10, 0, 4), 80 PIN_FIELD(0, 100, 0x0, 0x10, 0, 1), 84 PIN_FIELD(0, 100, 0x200, 0x10, 0, 1), 88 PIN_FIELD(0, 100, 0x100, 0x10, 0, 1), 92 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), 93 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), [all …]
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H A D | pinctrl-mt6779.c | 13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000, 14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, 15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000 21 32, 0) 28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4), 29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4), 30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4), 31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4), 32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4), 33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4), [all …]
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H A D | pinctrl-mt8195.c | 13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000, 14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000, 15 * iocfg[6]:0x11f40000. 21 32, 0) 28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4), 32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1), 36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1), 40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1), 44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1), 45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1), [all …]
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H A D | pinctrl-mt8192.c | 13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000, 14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000, 15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000, 16 * iocfg_tl:0x11F30000 22 32, 0) 29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4), 33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1), 37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1), 41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1), 45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1), [all …]
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H A D | pinctrl-mt8188.c | 13 * iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000, 14 * iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000 20 32, 0) 27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4), 31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1), 35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1), 39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1), 43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1), 44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1), 45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1), [all …]
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