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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dqcom-pm8xxx-rtc.yaml66 reg = <0x0c440000 0x1100>;
68 #size-cells = <0>;
69 pmicintc: pmic@0 {
70 reg = <0x0 SPMI_USID>;
76 #size-cells = <0>;
80 reg = <0x11d>;
81 interrupts = <0x27 0>;
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-pm8xxx.c24 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
27 #define NUM_8_BIT_RTC_REGS 0x4
94 return 0; in pm8xxx_rtc_read_nvmem_offset()
105 if (rc < 0) { in pm8xxx_rtc_write_nvmem_offset()
110 return 0; in pm8xxx_rtc_write_nvmem_offset()
116 return 0; in pm8xxx_rtc_read_offset()
137 if (rc < 0) in pm8xxx_rtc_read_raw()
140 if (reg < value[0]) { in pm8xxx_rtc_read_raw()
149 return 0; in pm8xxx_rtc_read_raw()
168 return 0; in pm8xxx_rtc_update_offset()
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/nds32/n13/
H A Datcpmu.json4 "EventCode": "0x102",
10 "EventCode": "0x103",
16 "EventCode": "0x104",
22 "EventCode": "0x105",
28 "EventCode": "0x106",
34 "EventCode": "0x107",
40 "EventCode": "0x108",
46 "EventCode": "0x109",
52 "EventCode": "0x10a",
58 "EventCode": "0x10b",
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h2 #define QLA_MODEL_NAMES 0x5C
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/openbmc/linux/drivers/perf/arm_cspmu/
H A Dnvidia_cspmu.c14 #define NV_PCIE_FILTER_ID_MASK GENMASK_ULL(NV_PCIE_PORT_COUNT - 1, 0)
17 #define NV_NVL_C2C_FILTER_ID_MASK GENMASK_ULL(NV_NVL_C2C_PORT_COUNT - 1, 0)
20 #define NV_CNVL_FILTER_ID_MASK GENMASK_ULL(NV_CNVL_PORT_COUNT - 1, 0)
22 #define NV_GENERIC_FILTER_ID_MASK GENMASK_ULL(31, 0)
24 #define NV_PRODID_MASK GENMASK(31, 0)
26 #define NV_FORMAT_NAME_GENERIC 0
48 ARM_CSPMU_EVENT_ATTR(bus_cycles, 0x1d),
50 ARM_CSPMU_EVENT_ATTR(scf_cache_allocate, 0xF0),
51 ARM_CSPMU_EVENT_ATTR(scf_cache_refill, 0xF1),
52 ARM_CSPMU_EVENT_ATTR(scf_cache, 0xF2),
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2057.h9 #define R2057_DACBUF_VINCM_CORE0 0x000
10 #define R2057_IDCODE 0x001
11 #define R2057_RCCAL_MASTER 0x002
12 #define R2057_RCCAL_CAP_SIZE 0x003
13 #define R2057_RCAL_CONFIG 0x004
14 #define R2057_GPAIO_CONFIG 0x005
15 #define R2057_GPAIO_SEL1 0x006
16 #define R2057_GPAIO_SEL0 0x007
17 #define R2057_CLPO_CONFIG 0x008
18 #define R2057_BANDGAP_CONFIG 0x009
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304>;
23 cpu@0 {
27 reg = <0>;
52 reg = <0x0 0x0>;
57 interrupts = <GIC_PPI 10 0x304>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
103 reg = <0x02000000 0x1000>,
[all …]
H A Dqcom-mdm9615.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0>;
45 #clock-cells = <0>;
66 reg = <0x02040000 0x1000>;
67 arm,data-latency = <2 2 0>;
76 reg = <0x02000000 0x1000>,
77 <0x02002000 0x1000>;
86 reg = <0x0200a000 0x100>;
88 cpu-offset = <0x80000>;
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dttable_64.S17 tl0_resv000: BOOT_KERNEL BTRAP(0x1) BTRAP(0x2) BTRAP(0x3)
18 tl0_resv004: BTRAP(0x4) BTRAP(0x5) BTRAP(0x6) BTRAP(0x7)
24 tl0_resv00b: BTRAP(0xb) BTRAP(0xc) BTRAP(0xd) BTRAP(0xe) BTRAP(0xf)
28 tl0_resv012: BTRAP(0x12) BTRAP(0x13) BTRAP(0x14) BTRAP(0x15) BTRAP(0x16) BTRAP(0x17)
29 tl0_resv018: BTRAP(0x18) BTRAP(0x19)
31 tl0_resv01b: BTRAP(0x1b)
32 tl0_resv01c: BTRAP(0x1c) BTRAP(0x1d) BTRAP(0x1e) BTRAP(0x1f)
39 tl0_resv029: BTRAP(0x29) BTRAP(0x2a) BTRAP(0x2b) BTRAP(0x2c) BTRAP(0x2d) BTRAP(0x2e)
40 tl0_resv02f: BTRAP(0x2f)
45 tl0_resv033: BTRAP(0x33)
[all …]
/openbmc/linux/sound/drivers/opl4/
H A Dyrw801.c40 snd_opl4_read_memory(opl4, buf, 0x001200, 15); in snd_yrw801_detect()
43 snd_opl4_read_memory(opl4, buf, 0x1ffffe, 2); in snd_yrw801_detect()
44 if (buf[0] != 0x01) in snd_yrw801_detect()
46 snd_printdd("YRW801 ROM version %02x.%02x\n", buf[0], buf[1]); in snd_yrw801_detect()
47 return 0; in snd_yrw801_detect()
58 {0x14, 0x27, {0x12c,7474,100, 0,0,0x00,0xc8,0x20,0xf2,0x13,0x08,0x0}},
59 {0x28, 0x2d, {0x12d,6816,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
60 {0x2e, 0x33, {0x12e,5899,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
61 {0x34, 0x39, {0x12f,5290,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
62 {0x3a, 0x3f, {0x130,4260,100, 0,0,0x0a,0xc8,0x20,0xf2,0x14,0x08,0x0}},
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dcore-imp-def.json4 "EventCode": "0x10A",
10 "EventCode": "0x10B",
16 "EventCode": "0x110",
22 "EventCode": "0x111",
28 "EventCode": "0x112",
34 "EventCode": "0x113",
40 "EventCode": "0x114",
46 "EventCode": "0x115",
52 "EventCode": "0x116",
58 "EventCode": "0x117",
[all …]
/openbmc/linux/crypto/async_tx/
H A Dasync_pq.c49 int src_off = 0; in do_async_gen_syndrome()
51 while (src_cnt > 0) { in do_async_gen_syndrome()
76 dma_dest[0] = unmap->addr[disks - 2]; in do_async_gen_syndrome()
119 for (i = 0; i < disks; i++) { in do_sync_gen_syndrome()
135 if (start >= 0) in do_sync_gen_syndrome()
148 for (i = 0; i < src_cnt; i++) { in is_dma_pq_aligned_offs()
149 if (!is_dma_pq_aligned(dev, offs[i], 0, len)) in is_dma_pq_aligned_offs()
157 * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1
164 * primitive polynomial of 0x11d and a generator of {02}.
194 (src_cnt <= dma_maxpq(device, 0) || in async_gen_syndrome()
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_radio.h9 #define RADIO_IDCODE 0x01
11 #define RADIO_DEFAULT_CORE 0
13 #define RXC0_RSSI_RST 0x80
14 #define RXC0_MODE_RSSI 0x40
15 #define RXC0_MODE_OFF 0x20
16 #define RXC0_MODE_CM 0x10
17 #define RXC0_LAN_LOAD 0x08
18 #define RXC0_OFF_ADJ_MASK 0x07
20 #define TXC0_MODE_TXLPF 0x04
21 #define TXC0_PA_TSSI_EN 0x02
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
[all …]
/openbmc/linux/lib/reed_solomon/
H A Dtest_rslib.c47 {2, 0x7, 1, 1, 1, 100000 },
48 {3, 0xb, 1, 1, 2, 100000 },
49 {3, 0xb, 1, 1, 3, 100000 },
50 {3, 0xb, 2, 1, 4, 100000 },
51 {4, 0x13, 1, 1, 4, 10000 },
52 {5, 0x25, 1, 1, 6, 1000 },
53 {6, 0x43, 3, 1, 8, 1000 },
54 {7, 0x89, 1, 1, 14, 500 },
55 {8, 0x11d, 1, 1, 30, 100 },
56 {8, 0x187, 112, 11, 32, 100 },
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dtable.c7 0x01c, 0x07000000,
8 0x800, 0x00040000,
9 0x804, 0x00008003,
10 0x808, 0x0000fc00,
11 0x80c, 0x0000000a,
12 0x810, 0x10005088,
13 0x814, 0x020c3d10,
14 0x818, 0x00200185,
15 0x81c, 0x00000000,
16 0x820, 0x01000000,
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Dsor.h9 #define SOR_CTXSW 0x00
11 #define SOR_SUPER_STATE0 0x01
13 #define SOR_SUPER_STATE1 0x02
16 #define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
17 #define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0)
18 #define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
19 #define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
21 #define SOR_STATE0 0x03
23 #define SOR_STATE1 0x04
24 #define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
[all …]
/openbmc/linux/drivers/net/wan/
H A Dhd64572.h4 * CPU modes 0 & 2.
15 * PC300 initial CVS version (3.4.0-pre1)
25 #define ILAR 0x00
28 #define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */
29 #define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */
30 #define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */
31 #define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */
32 #define WCRL 0x24 /* Wait Control Register L */
33 #define WCRM 0x25 /* Wait Control Register M */
34 #define WCRH 0x26 /* Wait Control Register H */
[all …]
/openbmc/linux/fs/pstore/
H A Dram_core.c40 #define PERSISTENT_RAM_SIG (0x43474244) /* DBGC */
57 unsigned long flags = 0; in buffer_start_add()
79 unsigned long flags = 0; in buffer_size_add()
104 memset(prz->ecc_info.par, 0, in persistent_ram_encode_rs8()
105 prz->ecc_info.ecc_size * sizeof(prz->ecc_info.par[0])); in persistent_ram_encode_rs8()
106 encode_rs8(prz->rs_decoder, data, len, prz->ecc_info.par, 0); in persistent_ram_encode_rs8()
107 for (i = 0; i < prz->ecc_info.ecc_size; i++) in persistent_ram_encode_rs8()
116 for (i = 0; i < prz->ecc_info.ecc_size; i++) in persistent_ram_decode_rs8()
119 NULL, 0, NULL, 0, NULL); in persistent_ram_decode_rs8()
176 if (numerr > 0) { in persistent_ram_ecc_old()
[all …]
/openbmc/linux/Documentation/fb/
H A Dmatroxfb.rst31 pass to the kernel this command line: "video=matroxfb:vesa:0x1BB".
35 unless you have primary display on non-Matrox VBE2.0 device (see
48 4 0x12 0x102
49 8 0x100 0x101 0x180 0x103 0x188
50 15 0x110 0x181 0x113 0x189
51 16 0x111 0x182 0x114 0x18A
52 24 0x1B2 0x184 0x1B5 0x18C
53 32 0x112 0x183 0x115 0x18B
63 4 0x104 0x106
64 8 0x105 0x190 0x107 0x198 0x11C
[all …]

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