Searched +full:0 +full:x11c20000 (Results 1 – 11 of 11) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | mediatek,mt8192-pinctrl.yaml | 149 reg = <0x10005000 0x1000>, 150 <0x11c20000 0x1000>, 151 <0x11d10000 0x1000>, 152 <0x11d30000 0x1000>, 153 <0x11d40000 0x1000>, 154 <0x11e20000 0x1000>, 155 <0x11e70000 0x1000>, 156 <0x11ea0000 0x1000>, 157 <0x11f20000 0x1000>, 158 <0x11f30000 0x1000>, [all …]
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H A D | mediatek,mt6779-pinctrl.yaml | 114 '-[0-9]*$': 158 enum: [0, 1] 165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 170 enum: [0, 1, 2, 3] 177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. 182 enum: [0, 1, 2, 3] [all …]
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/openbmc/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt6779.dtsi | 26 #size-cells = <0>; 28 cpu0: cpu@0 { 32 reg = <0x000>; 39 reg = <0x100>; 46 reg = <0x200>; 53 reg = <0x300>; 60 reg = <0x400>; 67 reg = <0x500>; 74 reg = <0x600>; 81 reg = <0x700>; [all …]
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H A D | mt7986a.dtsi | 21 #size-cells = <0>; 22 cpu0: cpu@0 { 24 reg = <0x0>; 32 reg = <0x1>; 40 reg = <0x2>; 48 reg = <0x3>; 58 #clock-cells = <0>; 73 reg = <0 0x43000000 0 0x30000>; 79 reg = <0 0x4fc00000 0 0x00100000>; 83 reg = <0 0x4fd00000 0 0x40000>; [all …]
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H A D | mt8192.dtsi | 34 #clock-cells = <0>; 43 #clock-cells = <0>; 50 #clock-cells = <0>; 57 #size-cells = <0>; 59 cpu0: cpu@0 { 62 reg = <0x000>; 73 performance-domains = <&performance 0>; 80 reg = <0x100>; 91 performance-domains = <&performance 0>; 98 reg = <0x200>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos850.dtsi | 52 #clock-cells = <0>; 57 #size-cells = <0>; 91 cpu0: cpu@0 { 94 reg = <0x0>; 100 reg = <0x1>; 106 reg = <0x2>; 112 reg = <0x3>; 118 reg = <0x100>; 124 reg = <0x101>; 130 reg = <0x102>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/renesas/ |
H A D | r9a07g043.dtsi | 17 #clock-cells = <0>; 19 clock-frequency = <0>; 24 #clock-cells = <0>; 26 clock-frequency = <0>; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 39 #clock-cells = <0>; 41 clock-frequency = <0>; 44 cluster0_opp: opp-table-0 { 80 reg = <0 0x10001200 0 0xb00>; [all …]
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H A D | r9a07g054.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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H A D | r9a07g044.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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/openbmc/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt6779.c | 13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000, 14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, 15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000 21 32, 0) 28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4), 29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4), 30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4), 31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4), 32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4), 33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4), [all …]
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H A D | pinctrl-mt8192.c | 13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000, 14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000, 15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000, 16 * iocfg_tl:0x11F30000 22 32, 0) 29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4), 33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1), 37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1), 41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1), 45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1), [all …]
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