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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,fimd.yaml65 default: 0
78 default: 0
85 default: 0
130 const: 0
133 "^port@[0-4]+$":
137 0 - for CAMIF0 input,
172 reg = <0x11c00000 0x20000>;
174 interrupts = <11 0>, <11 1>, <11 2>;
182 #size-cells = <0>;
187 pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8188-pinctrl.yaml188 reg = <0x10005000 0x1000>,
189 <0x11c00000 0x1000>,
190 <0x11e10000 0x1000>,
191 <0x11e20000 0x1000>,
192 <0x11ea0000 0x1000>,
193 <0x1000b000 0x1000>;
199 gpio-ranges = <&pio 0 0 176>;
201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt7981-pinctrl.yaml85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
396 enum: [0, 1, 2, 3]
400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4210-universal_c210.dts23 cs-gpios = <&gpy4 3 0>;
24 gpio-sck = <&gpy3 1 0>;
25 gpio-mosi = <&gpy3 3 0>;
26 gpio-miso = <&gpy3 0 0>;
28 cs@0 {
34 reg = <0x11c00000 0xa4>;
42 samsung,vl-clkp = <0>;
43 samsung,vl-oep = <0>;
55 samsung,vl-cmd-allow-len = <0xf>;
60 samsung,winid = <0>;
[all …]
H A Dexynos4210-trats.dts28 reg = <0x11c00000 0xa4>;
36 samsung,vl-clkp = <0>;
37 samsung,vl-oep = <0>;
49 samsung,vl-cmd-allow-len = <0xf>;
59 samsung,resolution = <0>;
60 samsung,rgb-mode = <0>;
65 reg = <0x11c80000 0x5c>;
68 samsung,dsim-config-e-virtual-ch = <0>;
72 samsung,dsim-config-e-byte-clk = <0>;
81 samsung,dsim-config-stop-holding-cnt = <0x7ff>;
[all …]
H A Dexynos4412-trats2.dts31 gpios = <&gpf1 5 0>, /* sda */
32 <&gpf1 4 0>; /* scl */
39 gpio = <&gpm2 0 0>, /* sda */
40 <&gpm2 1 0>; /* scl */
47 reg = <0x11c00000 0xa4>;
55 samsung,vl-clkp = <0>;
56 samsung,vl-oep = <0>;
68 samsung,vl-cmd-allow-len = <0xf>;
70 samsung,winid = <0>;
78 samsung,resolution = <0>;
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
100 reg = <0x1>;
106 reg = <0x2>;
112 reg = <0x3>;
118 reg = <0x100>;
124 reg = <0x101>;
130 reg = <0x102>;
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
[all …]
H A Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/openbmc/qemu/hw/arm/
H A Dexynos4210.c41 #define EXYNOS4210_CHIPID_ADDR 0x10000000
44 #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000
47 #define EXYNOS4210_RTC_BASE_ADDR 0x10070000
50 #define EXYNOS4210_MCT_BASE_ADDR 0x10050000
53 #define EXYNOS4210_I2C_SHIFT 0x00010000
54 #define EXYNOS4210_I2C_BASE_ADDR 0x13860000
60 #define EXYNOS4210_UART0_BASE_ADDR 0x13800000
61 #define EXYNOS4210_UART1_BASE_ADDR 0x13810000
62 #define EXYNOS4210_UART2_BASE_ADDR 0x13820000
63 #define EXYNOS4210_UART3_BASE_ADDR 0x13830000
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos850.c34 /* Register Offset definitions for CMU_TOP (0x120e0000) */
35 #define PLL_LOCKTIME_PLL_MMC 0x0000
36 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
37 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
38 #define PLL_CON0_PLL_MMC 0x0100
39 #define PLL_CON3_PLL_MMC 0x010c
40 #define PLL_CON0_PLL_SHARED0 0x0140
41 #define PLL_CON3_PLL_SHARED0 0x014c
42 #define PLL_CON0_PLL_SHARED1 0x0180
43 #define PLL_CON3_PLL_SHARED1 0x018c
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8188.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000,
14 * iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000
20 32, 0)
27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4),
31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1),
35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1),
39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1),
43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1),
44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1),
45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1),
[all …]