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Searched +full:0 +full:x11030000 (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/configs/
H A Devb-rk3229_defconfig3 CONFIG_SYS_TEXT_BASE=0x60000000
6 CONFIG_SYS_MALLOC_F_LEN=0x800
10 CONFIG_DEBUG_UART_BASE=0x11030000
12 CONFIG_SPL_STACK_R_ADDR=0x80000
19 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
26 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks as…
36 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
55 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
56 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk322x-board-spl.c23 #define GRF_BASE 0x11000000
24 #define SGRF_BASE 0x10140000
26 #define DEBUG_UART_BASE 0x11030000
34 GPIO1B2_GPIO = 0, in board_debug_uart_init()
40 GPIO1B1_GPIO = 0, in board_debug_uart_init()
47 CON_IOMUX_UART2SEL_2 = 0, in board_debug_uart_init()
62 #define SGRF_DDR_CON0 0x10150000
73 * printhex8(0x1234); in board_init_f()
87 ret = uclass_get_device(UCLASS_RAM, 0, &dev); in board_init_f()
94 rk_clrreg(SGRF_DDR_CON0, 0x4000); in board_init_f()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-pinctrl.yaml58 E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
109 $ref: "#/additionalProperties/anyOf/0"
133 reg = <0x11030000 0x10000>;
137 gpio-ranges = <&pinctrl 0 0 392>;
147 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
158 gpios = <RZG2L_GPIO(39, 2) 0>;
165 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
/openbmc/u-boot/arch/arm/dts/
H A Drk322x.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
48 reg = <0xf01>;
55 reg = <0xf02>;
62 reg = <0xf03>;
75 reg = <0x110f0000 0x4000>;
76 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 #clock-cells = <0>;
112 reg = <0x10080000 0x9000>;
115 ranges = <0 0x10080000 0x9000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi26 #size-cells = <0>;
31 reg = <0xf00>;
43 reg = <0xf01>;
53 reg = <0xf02>;
63 reg = <0xf03>;
71 cpu0_opp_table: opp-table-0 {
127 #clock-cells = <0>;
137 reg = <0x100b0000 0x4000>;
144 pinctrl-0 = <&i2s1_bus>;
150 reg = <0x100c0000 0x4000>;
[all …]