Home
last modified time | relevance | path

Searched +full:0 +full:x10d10000 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dintel,agilex5-clkmgr.yaml37 reg = <0x10d10000 0x1000>;
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5250.dtsi21 reg = <0x11400000 0x1000>;
22 interrupts = <0 46 0>;
27 interrupts = <0 32 0>;
33 reg = <0x13400000 0x1000>;
34 interrupts = <0 45 0>;
39 reg = <0x10d10000 0x1000>;
40 interrupts = <0 50 0>;
45 reg = <0x03860000 0x1000>;
46 interrupts = <0 47 0>;
51 reg = <0x12CA0000 0x100>;
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0c>;
92 reg = <0x10060000 0x100>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi23 service_reserved: svcbuffer@0 {
25 reg = <0x0 0x80000000 0x0 0x2000000>;
26 alignment = <0x1000>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
37 reg = <0x0>;
44 reg = <0x100>;
51 reg = <0x200>;
58 reg = <0x300>;
71 reg = <0x0 0x1d000000 0 0x10000>,
[all …]