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/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dmediatek,mt76.yaml136 "^r[0-9]+":
157 "^b[0-9]+$":
227 wifi@0,0 {
229 reg = <0x0000 0 0 0 0>;
231 mediatek,mtd-eeprom = <&factory 0x8000>;
266 reg = <0x10300000 0x100000>;
280 reg = <0x10300000 0x100000>;
293 reg = <0x18000000 0x1000000>,
294 <0x10003000 0x1000>,
295 <0x11d10000 0x1000>;
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl8712_spec.h17 #define RTL8712_IOBASE_TXPKT 0x10200000 /*IOBASE_TXPKT*/
18 #define RTL8712_IOBASE_RXPKT 0x10210000 /*IOBASE_RXPKT*/
19 #define RTL8712_IOBASE_RXCMD 0x10220000 /*IOBASE_RXCMD*/
20 #define RTL8712_IOBASE_TXSTATUS 0x10230000 /*IOBASE_TXSTATUS*/
21 #define RTL8712_IOBASE_RXSTATUS 0x10240000 /*IOBASE_RXSTATUS*/
22 #define RTL8712_IOBASE_IOREG 0x10250000 /*IOBASE_IOREG ADDR*/
23 #define RTL8712_IOBASE_SCHEDULER 0x10260000 /*IOBASE_SCHEDULE*/
25 #define RTL8712_IOBASE_TRXDMA 0x10270000 /*IOBASE_TRXDMA*/
26 #define RTL8712_IOBASE_TXLLT 0x10280000 /*IOBASE_TXLLT*/
27 #define RTL8712_IOBASE_WMAC 0x10290000 /*IOBASE_WMAC*/
[all …]
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/openbmc/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drv1108.dtsi28 #size-cells = <0>;
33 reg = <0xf00>;
53 #clock-cells = <0>;
64 reg = <0x102a0000 0x4000>;
65 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
75 reg = <0x10080000 0x2000>;
78 ranges = <0 0x10080000 0x2000>;
83 reg = <0x10210000 0x100>;
91 pinctrl-0 = <&uart2m0_xfer>;
97 reg = <0x10220000 0x100>;
[all …]
/openbmc/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1108.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
43 cpu_opp_table: opp-table-0 {
85 #clock-cells = <0>;
90 reg = <0x10080000 0x2000>;
93 ranges = <0 0x10080000 0x2000>;
98 reg = <0x10210000 0x100>;
107 pinctrl-0 = <&uart2m0_xfer>;
113 reg = <0x10220000 0x100>;
122 pinctrl-0 = <&uart1_xfer>;
[all …]