Searched +full:0 +full:x101c0000 (Results 1 – 14 of 14) sorted by relevance
8 cpu@0 {14 #address-cells = <0>;22 reg = <0x10000000 0x200000>;23 ranges = <0x0 0x10000000 0x1FFFFF>;28 sysc@0 {30 reg = <0x0 0x100>;35 reg = <0x200 0x100>;46 reg = <0x300 0x100>;51 reg = <0xc00 0x100>;62 reg = <0x101c0000 40000>;
10 #size-cells = <0>;12 cpu@0 {15 reg = <0>;25 #address-cells = <0>;33 reg = <0x10000000 0x200000>;34 ranges = <0x0 0x10000000 0x1FFFFF>;39 sysc: system-controller@0 {41 reg = <0x0 0x60>;46 reg = <0x60 0x8>;48 #size-cells = <0>;[all …]
10 #size-cells = <0>;12 cpu@0 {15 reg = <0>;25 #address-cells = <0>;33 reg = <0x10000000 0x200000>;34 ranges = <0x0 0x10000000 0x1FFFFF>;39 sysc: system-controller@0 {41 reg = <0x0 0x100>;47 offset = <0x34>;48 mask = <0x1>;[all …]
15 #define RT3883_SDRAM_BASE 0x0000000016 #define RT3883_SYSC_BASE IOMEM(0x10000000)17 #define RT3883_TIMER_BASE 0x1000010018 #define RT3883_INTC_BASE 0x1000020019 #define RT3883_MEMC_BASE 0x1000030020 #define RT3883_UART0_BASE 0x1000050021 #define RT3883_PIO_BASE 0x1000060022 #define RT3883_FSCC_BASE 0x1000070023 #define RT3883_NANDC_BASE 0x1000081024 #define RT3883_I2C_BASE 0x10000900[all …]
42 <7 0>,60 reg = <0x02020000 0x54000>;63 ranges = <0 0x02020000 0x54000>;65 smp-sram@0 {67 reg = <0x0 0x1000>;72 reg = <0x53000 0x1000>;79 reg = <0x101c0000 0xb00>;96 reg = <0x101d0000 0x100>;102 reg = <0x12d10000 0x100>;111 reg = <0x12ca0000 0x1000>;[all …]
47 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;80 cpu0_opp_table: opp-table-0 {176 reg = <0x02020000 0x30000>;179 ranges = <0 0x02020000 0x30000>;181 smp-sram@0 {183 reg = <0x0 0x1000>;188 reg = <0x2f000 0x1000>;194 reg = <0x10044000 0x20>;[all …]
67 0: Global Timer Interrupt 071 4: Local Timer Interrupt 0164 reg = <0x10050000 0x800>;184 reg = <0x101C0000 0x800>;205 reg = <0x10050000 0x800>;225 reg = <0x10050000 0x800>;
40 reg = <0x20018000 0x4000>;41 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,51 reg = <0x2001c000 0x4000>;52 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,63 reg = <0x20078000 0x4000>;76 #clock-cells = <0>;82 reg = <0x10138000 0x1000>;89 reg = <0x1013c000 0x100>;94 reg = <0x1013c200 0x20>;95 interrupts = <GIC_PPI 11 0x304>;[all …]
29 reg = <0x60000000 0x40000000>;41 #size-cells = <0>;47 reg = <0xf00>;60 reg = <0xf01>;73 reg = <0x20078000 0x4000>;75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,87 #clock-cells = <0>;102 reg = <0x20000000 0x1000>;112 reg = <0x20060000 0x100>;120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;[all …]
39 reg = <0x60000000 0x40000000>;52 #size-cells = <0>;55 cpu0:cpu@0x000 {58 reg = <0x000>;68 cpu1:cpu@0x001 {71 reg = <0x001>;74 cpu2:cpu@0x002 {77 reg = <0x002>;80 cpu3:cpu@0x003 {83 reg = <0x003>;[all …]
35 #clock-cells = <0>;41 reg = <0x10090000 0x10000>;52 reg = <0x10104000 0x800>;64 reg = <0x10138000 0x1000>;71 reg = <0x1013c000 0x100>;76 reg = <0x1013c200 0x20>;90 reg = <0x1013c600 0x20>;99 reg = <0x1013d000 0x1000>,100 <0x1013c100 0x0100>;105 reg = <0x10124000 0x400>;[all …]
34 #size-cells = <0>;40 reg = <0xf00>;53 reg = <0xf01>;84 #clock-cells = <0>;89 reg = <0x10080000 0x2000>;92 ranges = <0 0x10080000 0x2000>;94 smp-sram@0 {96 reg = <0x00 0x10>;102 reg = <0x10090000 0x10000>;122 reg = <0x10108000 0x800>;[all …]
29 #size-cells = <0>;34 reg = <0xf00>;47 reg = <0xf01>;53 reg = <0xf02>;59 reg = <0xf03>;77 #clock-cells = <0>;82 reg = <0x100a0000 0x1000>;87 reg = <0x10139000 0x1000>,88 <0x1013a000 0x1000>,89 <0x1013c000 0x2000>,[all …]
48 #clock-cells = <0>;53 #size-cells = <0>;91 reg = <0x100>;96 i-cache-size = <0x8000>;99 d-cache-size = <0x8000>;109 reg = <0x101>;112 i-cache-size = <0x8000>;115 d-cache-size = <0x8000>;125 reg = <0x102>;128 i-cache-size = <0x8000>;[all …]