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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,dw-apb-ictl.txt20 - 0 maps to bit 0 of low interrupts,
22 - 32 maps to bit 0 of high interrupts,
30 reg = <0x3000 0xc00>;
40 reg = <0x10130000 0x1000>;
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dsd5203.dts18 bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
27 #size-cells = <0>;
32 reg = <0x0>;
38 reg = <0x30000000 0x8000000>;
49 reg = <0x10130000 0x1000>;
56 #clock-cells = <0>;
62 reg = <0x16002000 0x1000>;
70 reg = <0x16003000 0x1000>;
78 reg = <0x1600d000 0x1000>;
88 reg = <0x1600c000 0x1000>;
/openbmc/linux/arch/arm/mach-nomadik/
H A Dcpu-8815.c17 #define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
18 #define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
19 #define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
20 #define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
21 #define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
22 #define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
23 #define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
24 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
25 #define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
26 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Darm-pl08x.yaml109 reg = <0x10130000 0x1000>;
128 arm,primecell-periphid = <0x0003b080>;
129 reg = <0x67000000 0x1000>;
/openbmc/qemu/hw/arm/
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
73 ranges = <0x0 0x10000000 0x200>;
77 led@8,0 {
79 reg = <0x08 0x04>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi14 reg = <0x00000000 0x04000000>,
15 <0x08000000 0x04000000>;
20 reg = <0x10210000 0x1000>;
37 reg = <0x101e2000 0x1000>;
46 reg = <0x101e3000 0x1000>;
55 reg = <0x101e4000 0x80>;
62 gpio-bank = <0>;
63 gpio-ranges = <&pinctrl 0 0 32>;
69 reg = <0x101e5000 0x80>;
77 gpio-ranges = <&pinctrl 0 32 32>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]