| /openbmc/linux/tools/testing/selftests/bpf/verifier/ |
| H A D | atomic_xor.c | 4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_xor(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x101) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x101, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_abm.c | 52 #define MCP_ABM_LEVEL_SET 0x65
53 #define MCP_ABM_PIPE_SET 0x66
54 #define MCP_BL_SET 0x67
61 uint32_t rampingBoundary = 0xFFFF; in dce_abm_set_pipe()
66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
93 unsigned int backlight_8_bit = 0; in dmcu_set_backlight_level()
96 if (backlight_pwm_u16_16 & 0x10000) in dmcu_set_backlight_level()
98 backlight_8_bit = 0xFF; in dmcu_set_backlight_level()
101 backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF; in dmcu_set_backlight_level()
[all …]
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| /openbmc/u-boot/cmd/aspeed/ |
| H A D | dptest.c | 18 #define MAINVER 0
33 #define DBG_ERR 0x00000001 /* DBG_ERROR */
34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */
35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */
36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */
37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */
38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */
39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */
40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */
41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */
[all …]
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| /openbmc/linux/include/linux/ |
| H A D | elfnote-lto.h | 6 #define LINUX_ELFNOTE_LTO_INFO 0x101
11 #define BUILD_LTO_INFO ELFNOTE32("Linux", LINUX_ELFNOTE_LTO_INFO, 0)
|
| /openbmc/u-boot/drivers/usb/emul/ |
| H A D | sandbox_keyb.c | 52 .bcdUSB = __constant_cpu_to_le16(0x0100),
54 .bDeviceClass = 0,
55 .bDeviceSubClass = 0,
56 .bDeviceProtocol = 0,
58 .idVendor = __constant_cpu_to_le16(0x1234),
59 .idProduct = __constant_cpu_to_le16(0x5679),
72 .bConfigurationValue = 0,
73 .iConfiguration = 0,
82 .bInterfaceNumber = 0,
83 .bAlternateSetting = 0,
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| H A D | clock.json | 8 "EventCode": "0x101",
14 "EventCode": "0x110",
|
| /openbmc/linux/drivers/of/unittest-data/ |
| H A D | overlay_bad_add_dup_node.dtso | 18 power_bus = <0x1 0x2>;
25 power_bus_emergency = <0x101 0x102>;
|
| /openbmc/u-boot/include/ |
| H A D | micrel.h | 3 #define MII_KSZ9021_EXT_COMMON_CTRL 0x100
4 #define MII_KSZ9021_EXT_STRAP_STATUS 0x101
5 #define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
6 #define MII_KSZ9021_EXT_OP_STRAP_STATUS 0x103
7 #define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
8 #define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
9 #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
10 #define MII_KSZ9021_EXT_ANALOG_TEST 0x107
12 #define MII_KSZ9031_MOD_REG 0x0000
14 #define MII_KSZ9031_MOD_DATA_NO_POST_INC 0x4000
[all …]
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| /openbmc/linux/arch/arm/probes/ |
| H A D | decode-arm.c | 19 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
21 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
72 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); in simulate_blx1()
79 int rm = insn & 0xf; in simulate_blx2bx()
85 regs->ARM_pc = rmv & ~0x1; in simulate_blx2bx()
87 if (rmv & 0x1) in simulate_blx2bx()
94 int rd = (insn >> 12) & 0xf; in simulate_mrs()
95 unsigned long mask = 0xf8ff03df; /* Mask out execution state */ in simulate_mrs()
119 /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
121 /* PLD (immediate) 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | multi-inno,mi0283qt.txt | 11 the panel interface mode (IM[3:0] pins):
13 - absent: IM=x101 3-wire 9-bit data serial interface
17 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
20 mi0283qt@0{
22 reg = <0>;
25 dc-gpios = <&gpio 25 0>;
|
| /openbmc/linux/include/soc/arc/ |
| H A D | timers.h | 12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
20 #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
23 #define ARC_TIMERN_MAX 0xFFFFFFFF
25 #define ARC_REG_TIMERS_BCR 0x75
|
| /openbmc/qemu/tests/qtest/ |
| H A D | tpm-emu.h | 16 #define TPM_RC_FAILURE 0x101
17 #define TPM2_ST_NO_SESSIONS 0x8001
20 #define TPM_TAG_RSP_COMMAND 0xc4
|
| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | ps3gpu.h | 16 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
17 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
19 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
20 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
21 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
22 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
39 head, ddr_offset, 0, 0); in lv1_gpu_display_sync()
47 head, ddr_offset, 0, 0); in lv1_gpu_display_flip()
55 xdr_lpar, xdr_size, ioif_offset, 0); in lv1_gpu_fb_setup()
70 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0, in lv1_gpu_fb_close()
[all …]
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| /openbmc/linux/arch/mips/sgi-ip22/ |
| H A D | ip22-mc.c | 35 …return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >=… in get_bank_size()
41 return bank % 2 ? res & 0xffff : res >> 16; in get_bank_config()
59 for (i = 0; i < 4; i++) { in probe_memory()
90 /* Step 0: Make sure we turn off the watchdog in case it's in sgimc_init()
103 sgimc->cstat = sgimc->gstat = 0; in sgimc_init()
120 tmp &= ~0xf; in sgimc_init()
121 tmp |= 0xd; in sgimc_init()
131 * 31 16 15 8 7 0 in sgimc_init()
136 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101 in sgimc_init()
138 sgimc->divider = 0x101; in sgimc_init()
[all …]
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| /openbmc/qemu/backends/tpm/ |
| H A D | tpm_int.h | 37 #define TPM_TAG_RQU_COMMAND 0xc1
38 #define TPM_TAG_RQU_AUTH1_COMMAND 0xc2
39 #define TPM_TAG_RQU_AUTH2_COMMAND 0xc3
41 #define TPM_TAG_RSP_COMMAND 0xc4
42 #define TPM_TAG_RSP_AUTH1_COMMAND 0xc5
43 #define TPM_TAG_RSP_AUTH2_COMMAND 0xc6
56 #define TPM_ORD_ContinueSelfTest 0x53
57 #define TPM_ORD_GetTicks 0xf1
58 #define TPM_ORD_GetCapability 0x65
60 #define TPM_CAP_PROPERTY 0x05
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-ap810-ap0-octa-core.dtsi | 13 #size-cells = <0>;
16 cpu0: cpu@0 {
19 reg = <0x000>;
25 reg = <0x001>;
31 reg = <0x100>;
37 reg = <0x101>;
43 reg = <0x200>;
49 reg = <0x201>;
55 reg = <0x300>;
61 reg = <0x301>;
|
| /openbmc/linux/drivers/media/rc/keymaps/ |
| H A D | rc-x96max.c | 13 { 0x140, KEY_POWER },
22 { 0x118, KEY_VOLUMEUP },
23 { 0x110, KEY_VOLUMEDOWN },
25 { 0x143, KEY_MUTE }, // config
27 { 0x100, KEY_EPG }, // mouse
28 { 0x119, KEY_BACK },
30 { 0x116, KEY_UP },
31 { 0x151, KEY_LEFT },
32 { 0x150, KEY_RIGHT },
33 { 0x11a, KEY_DOWN },
[all …]
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| /openbmc/openbmc-tools/adcapp/src/ |
| H A D | adc.h | 15 #define READ_ADC_CHANNEL _IOC(_IOC_WRITE,'K',0x100,0x3FFF)
16 #define READ_ADC_REF_VOLATGE _IOC(_IOC_WRITE,'K',0x101,0x3FFF)
17 #define READ_ADC_RESOLUTION _IOC(_IOC_WRITE,'K',0x102,0x3FFF)
18 #define ENABLE_EXT_REF_VOLTAGE _IOC(_IOC_WRITE,'K',0x103,0x3FFF)
19 #define DISABLE_EXT_REF_VOLTAGE _IOC(_IOC_WRITE,'K',0x104,0x3FFF)
20 #define ENABLE_ADC_CHANNEL _IOC(_IOC_WRITE,'K',0x105,0x3FFF)
21 #define DISABLE_ADC_CHANNEL _IOC(_IOC_WRITE,'K',0x106,0x3FFF)
31 #if 0
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | nvidia,tegra194-ccplex.yaml | 41 #size-cells = <0>;
43 cpu0_0: cpu@0 {
46 reg = <0x0>;
53 reg = <0x001>;
60 reg = <0x100>;
67 reg = <0x101>;
|
| H A D | cpus.yaml | 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
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| /openbmc/linux/arch/arm/boot/dts/microchip/ |
| H A D | usb_a9g20-dab-mmx.dtsi | 21 i2c-gpio@0 {
69 #size-cells = <0>;
74 linux,code = <0x100>;
80 linux,code = <0x101>;
86 linux,code = <0x102>;
92 linux,code = <0x103>;
|
| /openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray-pcie.dtsi | 8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
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| H A D | cpu-capacity.txt | 70 #size-cells = <0>;
101 CPU_SLEEP_0: cpu-sleep-0 {
103 arm,psci-suspend-param = <0x0010000>;
110 CLUSTER_SLEEP_0: cluster-sleep-0 {
112 arm,psci-suspend-param = <0x1010000>;
120 A57_0: cpu@0 {
122 reg = <0x0 0x0>;
126 clocks = <&scpi_dvfs 0>;
133 reg = <0x0 0x1>;
137 clocks = <&scpi_dvfs 0>;
[all …]
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-ap806-quad.dtsi | 55 #size-cells = <0>;
60 reg = <0x000>;
66 reg = <0x001>;
72 reg = <0x100>;
78 reg = <0x101>;
|