Searched +full:0 +full:x100a0000 (Results 1 – 13 of 13) sorted by relevance
/openbmc/linux/arch/mips/include/asm/sibyte/ |
H A D | bigsur.h | 19 #define LEDS_PHYS 0x100a0000 23 #define IDE_PHYS 0x100b0000 30 #define PCMCIA_PHYS 0x11000000
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H A D | swarm.h | 18 #define SIBYTE_HAVE_PCMCIA 0 24 #define SIBYTE_HAVE_PCMCIA 0 25 #define SIBYTE_HAVE_IDE 0 30 #define LEDS_PHYS 0x100a0000 34 #define IDE_PHYS 0x100b0000 41 #define PCMCIA_PHYS 0x11000000
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/openbmc/linux/Documentation/devicetree/bindings/input/ |
H A D | samsung-keypad.txt | 36 - pinctrl-0: Should specify pin control groups used for this controller. 50 reg = <0x100A0000 0x100>; 58 pinctrl-0 = <&keypad_rows &keypad_columns>; 61 keypad,row = <0>; 67 keypad,row = <0>; 73 keypad,row = <0>;
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/openbmc/linux/Documentation/devicetree/bindings/thermal/ |
H A D | samsung,exynos-thermal.yaml | 24 # For TMU channel 0, 1 on Exynos5420: 59 TRIMINFO at 0x1006c000 contains data for TMU channel 3 60 TRIMINFO at 0x100a0000 contains data for TMU channel 4 61 TRIMINFO at 0x10068000 contains data for TMU channel 2 150 reg = <0x100C0000 0x100>; 153 #thermal-sensor-cells = <0>; 164 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 166 #thermal-sensor-cells = <0>; 177 reg = <0x10060000 0x200>; 179 #thermal-sensor-cells = <0>;
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/openbmc/linux/arch/riscv/boot/dts/sifive/ |
H A D | fu540-c000.dtsi | 24 #size-cells = <0>; 25 cpu0: cpu@0 { 31 reg = <0>; 167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 168 reg = <0x0 0xc000000 0x0 0x4000000>; 169 #address-cells = <0>; 173 <&cpu0_intc 0xffffffff>, 174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, 175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, 176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, [all …]
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H A D | fu740-c000.dtsi | 24 #size-cells = <0>; 25 cpu0: cpu@0 { 32 reg = <0x0>; 56 reg = <0x1>; 80 reg = <0x2>; 104 reg = <0x3>; 128 reg = <0x4>; 169 #address-cells = <0>; 170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 171 reg = <0x0 0xc000000 0x0 0x4000000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5420.dtsi | 153 cluster_a15_opp_table: opp-table-0 { 270 reg = <0x10d20000 0x1000>; 271 ranges = <0x0 0x10d20000 0x6000>; 276 reg = <0x4000 0x1000>; 281 reg = <0x5000 0x1000>; 287 reg = <0x10010000 0x30000>; 293 reg = <0x03810000 0x0c>; 303 reg = <0x11000000 0x10000>; 316 #size-cells = <0>; 317 reg = <0x12200000 0x2000>; [all …]
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H A D | exynos4.dtsi | 68 reg = <0x03810000 0x0c>; 79 reg = <0x03830000 0x100>; 88 samsung,idma-addr = <0x03000000>; 95 reg = <0x10000000 0x100>; 100 reg = <0x10500000 0x2000>; 105 reg = <0x12570000 0x14>; 110 reg = <0x10023c40 0x20>; 111 #power-domain-cells = <0>; 117 reg = <0x10023c60 0x20>; 118 #power-domain-cells = <0>; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3128.dtsi | 39 reg = <0x60000000 0x40000000>; 52 #size-cells = <0>; 55 cpu0:cpu@0x000 { 58 reg = <0x000>; 68 cpu1:cpu@0x001 { 71 reg = <0x001>; 74 cpu2:cpu@0x002 { 77 reg = <0x002>; 80 cpu3:cpu@0x003 { 83 reg = <0x003>; [all …]
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/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3128.dtsi | 29 #size-cells = <0>; 34 reg = <0xf00>; 47 reg = <0xf01>; 53 reg = <0xf02>; 59 reg = <0xf03>; 77 #clock-cells = <0>; 82 reg = <0x100a0000 0x1000>; 87 reg = <0x10139000 0x1000>, 88 <0x1013a000 0x1000>, 89 <0x1013c000 0x2000>, [all …]
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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_main.c | 55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd.dtsi | 39 #size-cells = <0>; 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 92 reg = <0x0 0x000>; 96 i-cache-size = <0xc000>; 99 d-cache-size = <0x8000>; 108 reg = <0x0 0x001>; 112 i-cache-size = <0xc000>; 115 d-cache-size = <0x8000>; 124 reg = <0x0 0x002>; [all …]
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/openbmc/qemu/hw/riscv/ |
H A D | sifive_u.c | 10 * 0) UART 69 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 70 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 72 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 73 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 74 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 75 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 76 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 77 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, [all …]
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