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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dti,am65-pci-host.yaml88 reg = <0x5500000 0x1000>,
89 <0x5501000 0x1000>,
90 <0x10000000 0x2000>,
91 <0x5506000 0x1000>;
96 ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
97 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
98 ti,syscon-pcie-id = <&scm_conf 0x0210>;
99 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
100 bus-range = <0x0 0xff>;
104 msi-map = <0x0 &gic_its 0x0 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Daxxia-reset.txt14 reg = <0x20 0x10030000 0 0x2000>;
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dnetspace_v2.h15 #define NETSPACE_V2_OE_LOW 0x06004000
16 #define NETSPACE_V2_OE_HIGH 0x00000031
17 #define NETSPACE_V2_OE_VAL_LOW 0x10030000
18 #define NETSPACE_V2_OE_VAL_HIGH 0x00000000
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dnet2big_v2.h15 #define NET2BIG_V2_OE_LOW 0x0600E000
16 #define NET2BIG_V2_OE_HIGH 0x00000134
17 #define NET2BIG_V2_OE_VAL_LOW 0x10030000
18 #define NET2BIG_V2_OE_VAL_HIGH 0x00000000
24 #define G762_REG_SET_CNT 0x00
25 #define G762_REG_SET_OUT 0x03
26 #define G762_REG_FAN_CMD1 0x04
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/linux/arch/mips/boot/compressed/
H A Duart-16550.c12 #define UART_BASE 0x1fd003f8
22 #define INGENIC_UART_BASE_ADDR (0x10030000 + 0x1000 * CONFIG_ZBOOT_INGENIC_UART)
36 return *((volatile IOTYPE *)PORT(offset)) & 0xFF; in serial_in()
41 *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; in serial_out()
48 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0)) in putc()
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4x12.dtsi34 reg = <0x10023CA0 0x20>;
39 reg = <0x10030000 0x20000>;
45 reg = <0x10050000 0x800>;
47 interrupts = <0>, <1>, <2>, <3>, <4>;
53 #address-cells = <0>;
54 #size-cells = <0>;
55 interrupt-map = <0 &gic 0 57 0>,
59 <4 &gic 1 12 0>;
65 reg = <0x11400000 0x1000>;
67 interrupts = <0 47 0>;
[all …]
H A Dexynos4210.dtsi37 reg = <0x10023CA0 0x20>;
41 cpu-offset = <0x8000>;
46 reg = <0x10050000 0x800>;
48 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 interrupt-map = <0 &gic 0 57 0>,
57 <1 &gic 0 69 0>,
60 <4 &gic 0 42 0>,
61 <5 &gic 0 48 0>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Djz4780.dtsi11 #address-cells = <0>;
19 reg = <0x10001000 0x50>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 reg = <0x10000000 0x100>;
51 reg = <0x13450000 0x1000>;
61 reg = <0x13460000 0x1000>;
71 reg = <0x10030000 0x100>;
85 reg = <0x10031000 0x100>;
99 reg = <0x10032000 0x100>;
[all …]
/openbmc/qemu/hw/misc/
H A Dexynos4210_clk.c32 #define EXYNOS4210_CLK_REGS_MEM_SIZE 0x15104
40 /* Clock controller register base: 0x10030000 */
42 {"EPLL_LOCK", 0xc010, 0x00000fff},
43 {"VPLL_LOCK", 0xc020, 0x00000fff},
44 {"EPLL_CON0", 0xc110, 0x00300301 | CLK_PLL_LOCKED},
45 {"EPLL_CON1", 0xc114, 0x00000000},
46 {"VPLL_CON0", 0xc120, 0x00240201 | CLK_PLL_LOCKED},
47 {"VPLL_CON1", 0xc124, 0x66010464},
48 {"APLL_LOCK", 0x14000, 0x00000fff},
49 {"MPLL_LOCK", 0x14004, 0x00000fff},
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
/openbmc/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos850-clock.yaml301 reg = <0x10030000 0x8000>;
H A Dsamsung,exynos5433-clock.yaml62 # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
507 #clock-cells = <0>;
513 reg = <0x10030000 0x1000>;
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
168 reg = <0x0 0xc000000 0x0 0x4000000>;
169 #address-cells = <0>;
173 <&cpu0_intc 0xffffffff>,
174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]
H A Dexynos4x12.dtsi70 #interconnect-cells = <0>;
80 #interconnect-cells = <0>;
120 #interconnect-cells = <0>;
211 reg = <0x11400000 0x1000>;
217 reg = <0x11000000 0x1000>;
229 reg = <0x03860000 0x1000>;
231 interrupts = <10 0>;
236 reg = <0x106e0000 0x1000>;
242 reg = <0x02020000 0x40000>;
245 ranges = <0 0x02020000 0x40000>;
[all …]

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