Lines Matching +full:0 +full:x10030000
24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
175 <&cpu0_intc 0xffffffff>,
176 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
177 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
178 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
179 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
183 reg = <0x0 0x10000000 0x0 0x1000>;
190 reg = <0x0 0x10010000 0x0 0x1000>;
198 reg = <0x0 0x10011000 0x0 0x1000>;
206 reg = <0x0 0x10030000 0x0 0x1000>;
213 #size-cells = <0>;
218 reg = <0x0 0x10031000 0x0 0x1000>;
225 #size-cells = <0>;
230 reg = <0x0 0x10040000 0x0 0x1000>,
231 <0x0 0x20000000 0x0 0x10000000>;
236 #size-cells = <0>;
241 reg = <0x0 0x10041000 0x0 0x1000>,
242 <0x0 0x30000000 0x0 0x10000000>;
247 #size-cells = <0>;
252 reg = <0x0 0x10050000 0x0 0x1000>;
257 #size-cells = <0>;
264 reg = <0x0 0x10090000 0x0 0x2000>,
265 <0x0 0x100a0000 0x0 0x1000>;
271 #size-cells = <0>;
276 reg = <0x0 0x10020000 0x0 0x1000>;
285 reg = <0x0 0x10021000 0x0 0x1000>;
301 reg = <0x0 0x2010000 0x0 0x1000>;
309 reg = <0x0 0x10060000 0x0 0x1000>;
322 reg = <0xe 0x00000000 0x0 0x80000000>,
323 <0xd 0xf0000000 0x0 0x10000000>,
324 <0x0 0x100d0000 0x0 0x1000>;
328 bus-range = <0x0 0xff>;
329 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
330 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
331 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x10000000>, /* mem */
332 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
333 num-lanes = <0x8>;
337 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
338 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
339 <0x0 0x0 0x0 0x2 &plic0 58>,
340 <0x0 0x0 0x0 0x3 &plic0 59>,
341 <0x0 0x0 0x0 0x4 &plic0 60>;
344 pwren-gpios = <&gpio 5 0>;
345 reset-gpios = <&gpio 8 0>;