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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/u-boot/include/configs/
H A Dfpga_ast2600_spl.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
21 #define CONFIG_SPL_TEXT_BASE 0x00000000
22 #define CONFIG_SPL_MAX_SIZE 0x0000E800
23 #define CONFIG_SPL_STACK 0x10010000
25 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
26 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
H A Devb_ast2600a0_spl.h12 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
13 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
18 #define CONFIG_SYS_LOAD_ADDR 0x83000000
29 #define CONFIG_SYS_MONITOR_LEN 0xe0000
32 #define CONFIG_SPL_TEXT_BASE 0x00000000
33 #define CONFIG_SPL_MAX_SIZE 0x0000E800
34 #define CONFIG_SPL_STACK 0x10010000
36 #define CONFIG_SPL_BSS_START_ADDR 0x90000000
37 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
H A Dstm32f429-discovery.h10 #define CONFIG_SYS_FLASH_BASE 0x08000000
12 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
17 #define CONFIG_SYS_LOAD_ADDR 0x90400000
18 #define CONFIG_LOADADDR 0x90400000
47 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
49 "bootm 0x08044000 - 0x08042000\0"
H A Dstm32f469-discovery.h10 #define CONFIG_SYS_FLASH_BASE 0x08000000
12 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
17 #define CONFIG_SYS_LOAD_ADDR 0x00400000
18 #define CONFIG_LOADADDR 0x00400000
41 func(MMC, mmc, 0)
45 "kernel_addr_r=0x00008000\0" \
46 "fdtfile=stm32f469-disco.dtb\0" \
47 "fdt_addr_r=0x00700000\0" \
48 "scriptaddr=0x00800000\0" \
49 "pxefile_addr_r=0x00800000\0" \
[all …]
H A Dstm32f429-evaluation.h10 #define CONFIG_SYS_FLASH_BASE 0x08000000
12 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
17 #define CONFIG_SYS_LOAD_ADDR 0x00400000
18 #define CONFIG_LOADADDR 0x00400000
41 func(MMC, mmc, 0)
45 "kernel_addr_r=0x00008000\0" \
46 "fdtfile=stm32429i-eval.dtb\0" \
47 "fdt_addr_r=0x00700000\0" \
48 "scriptaddr=0x00800000\0" \
49 "pxefile_addr_r=0x00800000\0" \
[all …]
H A Dembestmx6boards.h39 #define CONFIG_MXC_USB_FLAGS 0
42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
54 #define CONFIG_SYS_MEMTEST_START 0x10000000
55 #define CONFIG_SYS_MEMTEST_END 0x10010000
56 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
104 #define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
108 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */
109 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */
110 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */
117 "bootm_size=0x10000000\0" \
[all …]
H A Dnitrogen6x.h35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
43 #define CONFIG_DWC_AHSATA_PORT_ID 0
58 #define CONFIG_MXC_USB_FLAGS 0
74 #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
80 #define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
86 #define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
105 #define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
121 "console=ttymxc1\0" \
122 "fdt_high=0xffffffff\0" \
123 "initrd_high=0xffffffff\0" \
[all …]
H A Dmx6qarm2.h26 #define CONFIG_FEC_MXC_PHYADDR 0
29 "script=boot.scr\0" \
30 "image=zImage\0" \
31 "console=ttymxc3\0" \
32 "fdt_file=imx6q-arm2.dtb\0" \
33 "fdt_addr=0x18000000\0" \
34 "fdt_high=0xffffffff\0" \
35 "initrd_high=0xffffffff\0" \
36 "boot_fdt=try\0" \
37 "ip_dyn=yes\0" \
[all …]
H A Dge_bx50v3.h43 #define CONFIG_DWC_AHSATA_PORT_ID 0
50 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
57 #define CONFIG_MXC_USB_FLAGS 0
78 #define CONFIG_LOADADDR 0x12000000
81 "bootcause=POR\0" \
82 "image=/boot/fitImage\0" \
83 "fdt_high=0xffffffff\0" \
84 "dev=mmc\0" \
85 "devnum=1\0" \
86 "rootdev=mmcblk0p\0" \
[all …]
H A Dcgtqmx6eval.h31 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
52 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
57 #define CONFIG_MXC_USB_FLAGS 0
74 #define CONFIG_DWC_AHSATA_PORT_ID 0
91 #define CONFIG_SYS_MMC_ENV_DEV 0
94 "script=boot.scr\0" \
95 "image=zImage\0" \
96 "fdtfile=undefined\0" \
97 "fdt_addr_r=0x18000000\0" \
98 "boot_fdt=try\0" \
[all …]
H A Dmx6sabre_common.h21 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
33 "emmcdev=2\0" \
42 "setexpr fw_sz ${filesize} / 0x200; " \
44 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
46 "fi\0"
52 "script=boot.scr\0" \
53 "image=zImage\0" \
54 "fdt_file=undefined\0" \
55 "fdt_addr=0x18000000\0" \
56 "boot_fdt=try\0" \
[all …]
H A Dimx6_logic.h24 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
31 #define CONFIG_FEC_MXC_PHYADDR 0
34 "script=boot.scr\0" \
35 "image=zImage\0" \
36 "bootm_size=0x10000000\0" \
37 "fdt_addr_r=0x13000000\0" \
38 "ramdisk_addr_r=0x14000000\0" \
39 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
40 "ramdisk_file=rootfs.cpio.uboot\0" \
41 "boot_fdt=try\0" \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-clock.yaml58 reg = <0x10010000 0x30000>;
H A Dsamsung,exynos5410-clock.yaml58 #clock-cells = <0>;
63 reg = <0x10010000 0x30000>;
H A Dsamsung,exynos7885-clock.yaml168 reg = <0x10010000 0x8000>;
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml61 reg = <0x10010000 0x1000>;
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dmediatek,mt6779-keypad.yaml78 reg = <0 0x10010000 0 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dsamsung,exynos-sysreg.yaml86 reg = <0x10010000 0x400>;
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h9 #define OCRAM_BASE_ADDR 0x10000000
10 #define OCRAM_SIZE 0x00010000
11 #define OCRAM_BASE_S_ADDR 0x10010000
12 #define OCRAM_S_SIZE 0x00010000
14 #define CONFIG_SYS_IMMR 0x01000000
15 #define CONFIG_SYS_DCSRBAR 0x20000000
17 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
18 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
20 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
21 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
65 const: 0
68 "^gpio@[0-9]$":
170 reg = <0x10010000 0x600>;
173 #size-cells = <0>;
175 gpio@0 {
177 reg = <0>;
180 gpio-ranges = <&pinctrl 0 0 32>;
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/openbmc/qemu/hw/arm/
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
/openbmc/u-boot/test/lib/
H A Dlmb.c20 ut_asserteq(lmb->memory.region[0].base, ram_base); in check_lmb()
21 ut_asserteq(lmb->memory.region[0].size, ram_size); in check_lmb()
25 if (num_reserved > 0) { in check_lmb()
26 ut_asserteq(lmb->reserved.region[0].base, base1); in check_lmb()
27 ut_asserteq(lmb->reserved.region[0].size, size1); in check_lmb()
37 return 0; in check_lmb()
56 const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000; in test_multi_alloc()
63 ut_assert(ram_end == 0 || ram_end > ram); in test_multi_alloc()
73 ut_asserteq(ret, 0); in test_multi_alloc()
77 ut_asserteq(ret, 0); in test_multi_alloc()
[all …]

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