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/openbmc/linux/Documentation/devicetree/bindings/auxdisplay/
H A Darm,versatile-lcd.yaml43 reg = <0x10008000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dmediatek,mtk-timer.txt45 reg = <0x10008000 0x80>;
/openbmc/u-boot/include/configs/
H A Dimx6dl-mamoj.h29 # define CONFIG_ENV_OFFSET 0x100000
35 "scriptaddr=0x14000000\0" \
36 "fdt_addr_r=0x13000000\0" \
37 "kernel_addr_r=0x10008000\0" \
38 "fdt_high=0xffffffff\0" \
39 "dfu_alt_info_spl=spl raw 0x2 0x400\0" \
40 "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
62 #define CONFIG_MXC_USB_FLAGS 0
69 #define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
73 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
[all …]
H A Dkp_imx6q_tpc.h31 #define CONFIG_FEC_MXC_PHYADDR 0
49 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
51 #define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
65 #define CONFIG_MXC_USB_FLAGS 0
75 #define CONFIG_LOADADDR 0x12000000
80 "console=ttymxc0,115200\0" \
81 "fdt_addr=0x18000000\0" \
82 "fdt_high=0xffffffff\0" \
83 "initrd_high=0xffffffff\0" \
84 "kernel_addr_r=0x10008000\0" \
[all …]
H A Ddh_imx6.h17 * 0x00_0000-0x00_ffff ... U-Boot SPL
18 * 0x01_0000-0x0f_ffff ... U-Boot
19 * 0x10_0000-0x10_ffff ... U-Boot env #1
20 * 0x11_0000-0x11_ffff ... U-Boot env #2
21 * 0x12_0000-0x1f_ffff ... UNUSED
26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
48 #define CONFIG_FEC_MXC_PHYADDR 0
66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define CONFIG_DWC_AHSATA_PORT_ID 0
91 #define CONFIG_MXC_USB_FLAGS 0
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt6580.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10008000 0x80>;
[all …]
H A Dmt6582.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x2>;
37 reg = <0x3>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
61 reg = <0x10008000 0x80>;
[all …]
H A Dmt6589.dtsi19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
30 reg = <0x1>;
35 reg = <0x2>;
40 reg = <0x3>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
78 reg = <0x10008000 0x80>;
[all …]
H A Dmt6592.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
44 reg = <0x4>;
49 reg = <0x5>;
54 reg = <0x6>;
59 reg = <0x7>;
[all …]
H A Dmt8127.dtsi19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
30 reg = <0x1>;
35 reg = <0x2>;
40 reg = <0x3>;
52 reg = <0 0x80002000 0 0x1000>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
[all …]
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Driscv-virt-machine.c33 #define RISCV_VIRT_RAM_ADDR 0x80000000
34 #define RISCV_VIRT_RAM_SIZE 0x20000000
40 #define VIRTIO_MMIO_BASE_ADDR 0x10008000
41 #define VIRTIO_MMIO_SIZE 0x00001000
44 #define RISCV_GPEX_PIO_BASE 0x3000000
45 #define RISCV_BUS_PIO_LIMIT 0x10000
48 #define RISCV_BUS_MMIO_ALLOC_PTR 0x40000000
49 #define RISCV_BUS_MMIO_LIMIT 0x80000000
52 #define RISCV_ECAM_ALLOC_PTR 0x30000000
108 alloc_init(&machine->alloc, 0, in qos_create_machine_riscv_virt()
/openbmc/u-boot/common/
H A Dimage-android.c12 #define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
61 andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0'; in android_image_get_kernel()
65 printf("Kernel load addr 0x%08x size %u KiB\n", in android_image_get_kernel()
68 int len = 0; in android_image_get_kernel()
83 *newbootargs = '\0'; in android_image_get_kernel()
100 return 0; in android_image_get_kernel()
133 *rd_data = *rd_len = 0; in android_image_get_ramdisk()
137 printf("RAM disk load addr 0x%08x size %u KiB\n", in android_image_get_ramdisk()
145 return 0; in android_image_get_ramdisk()
152 *second_data = *second_len = 0; in android_image_get_second()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
40 reg = <0x1>;
50 reg = <0x2>;
60 reg = <0x3>;
71 #clock-cells = <0>;
76 #clock-cells = <0>;
81 clk26m: oscillator-0 {
83 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/riscv/
H A Dsifive_e.c8 * 0) UART
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
52 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
53 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
54 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
56 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
57 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
58 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
59 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
40 #size-cells = <0>;
42 port@0 {
43 reg = <0>;
72 reg = <0x10000000 0x200>;
73 ranges = <0x0 0x10000000 0x200>;
77 led@8,0 {
79 reg = <0x08 0x04>;
[all …]
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
81 #clock-cells = <0>;
89 #clock-cells = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 pclk: pclk@0 {
114 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
H A Dmt6795.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
35 reg = <0x000>;
44 reg = <0x001>;
59 reg = <0x002>;
74 reg = <0x003>;
89 reg = <0x100>;
104 reg = <0x101>;
119 reg = <0x102>;
134 reg = <0x103>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]

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