| /openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | other.json | 4 "EventCode": "0xc1",
7 "UMask": "0x4",
12 "EventCode": "0xc1",
15 "UMask": "0x8",
20 "EventCode": "0x28",
23 "UMask": "0x2",
28 "EventCode": "0x28",
31 "UMask": "0x4",
36 "EventCode": "0x28",
39 "UMask": "0x8",
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8ulp-evk.dts | 20 reg = <0x0 0x80000000 0 0x80000000>;
31 size = <0 0x28000000>;
36 reg = <0 0xa8600000 0 0x1000000>;
41 reg = <0 0x1fff8000 0 0x1000>;
46 reg = <0 0xaff00000 0 0x8000>;
51 reg = <0 0xaff08000 0 0x8000>;
56 reg = <0 0xaff10000 0 0x8000>;
61 reg = <0 0xaff18000 0 0x8000>;
67 reg = <0 0xa8400000 0 0x100000>;
76 #clock-cells = <0>;
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | other.json | 4 "EventCode": "0xB7",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10001",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x10002",
18 "UMask": "0x1"
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | other.json | 4 "EventCode": "0xB7",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10001",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x10002",
18 "UMask": "0x1"
|
| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | other.json | 4 "EventCode": "0xB7",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x10008",
9 "UMask": "0x1"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x10001",
18 "UMask": "0x1"
22 "EventCode": "0xB7",
24 "MSRIndex": "0x1a6,0x1a7",
[all …]
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/ |
| H A D | 0043-firmware-psci-Fix-bind_smccc_features-psci-check.patch | 25 PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0)
26 return 0;
31 return 0;
33 + if (invoke_psci_fn(ARM_SMCCC_VERSION, 0, 0, 0) < ARM_SMCCC_VERSION_1_1)
34 + return 0;
44 #define ARM_SMCCC_QUIRK_NONE 0
47 +#define ARM_SMCCC_VERSION 0x80000000
48 #define ARM_SMCCC_ARCH_FEATURES 0x80000001
50 +#define ARM_SMCCC_VERSION_1_0 0x10000
51 +#define ARM_SMCCC_VERSION_1_1 0x10001
[all …]
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| /openbmc/qemu/bsd-user/i386/ |
| H A D | target_arch_signal.h | 24 #define TARGET_SZSIGCODE 0
53 #define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */
54 #define _MC_FPFMT_387 0x10001
55 #define _MC_FPFMT_XMM 0x10002
57 #define _MC_FPOWNED_NONE 0x20000 /* FP state not used */
58 #define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */
59 #define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */
|
| /openbmc/qemu/bsd-user/x86_64/ |
| H A D | target_arch_signal.h | 25 #define TARGET_SZSIGCODE 0
64 #define _MC_FPFMT_NODEV 0x10000 /* device not present or configured */
65 #define _MC_FPFMT_XMM 0x10002
67 #define _MC_FPOWNED_NONE 0x20000 /* FP state not used */
68 #define _MC_FPOWNED_FPU 0x20001 /* FP state came from FPU */
69 #define _MC_FPOWNED_PCB 0x20002 /* FP state came from PCB */
|
| /openbmc/u-boot/tools/ |
| H A D | mtk_image.h | 22 uint8_t pad[0x200];
47 uint8_t data[0x80];
68 #define BRLYT_MAGIC 0x42424242
71 BRLYT_TYPE_INVALID = 0,
72 BRLYT_TYPE_NAND = 0x10002,
73 BRLYT_TYPE_EMMC = 0x10005,
74 BRLYT_TYPE_NOR = 0x10007,
75 BRLYT_TYPE_SDMMC = 0x10008,
76 BRLYT_TYPE_SNAND = 0x10009
85 uint8_t brlyt_pad[0x400];
[all …]
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| /openbmc/linux/tools/include/linux/ |
| H A D | arm-smccc.h | 18 #define ARM_SMCCC_STD_CALL _AC(0,U)
22 #define ARM_SMCCC_SMC_32 0
26 #define ARM_SMCCC_OWNER_MASK 0x3F
29 #define ARM_SMCCC_FUNC_MASK 0xFFFF
45 #define ARM_SMCCC_OWNER_ARCH 0
57 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
59 #define ARM_SMCCC_QUIRK_NONE 0
62 #define ARM_SMCCC_VERSION_1_0 0x10000
63 #define ARM_SMCCC_VERSION_1_1 0x10001
64 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | hns3-pmu.rst | 44 config=0x00204
46 config=0x10204
51 The bits 0~15 of config (here 0x0204) are the true hardware event code. If
52 two events have same value of bits 0~15 of config, that means they are
53 event pair. And the bit 16 of config indicates getting counter 0 or
59 counter 0 / counter 1
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
90 is same as mac id. The "tc" filter option must be set to 0xF in this mode,
95 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
[all …]
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| /openbmc/linux/drivers/media/platform/qcom/venus/ |
| H A D | hfi_cmds.h | 12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
[all …]
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| /openbmc/linux/include/uapi/linux/ |
| H A D | dlmconstants.h | 31 #define DLM_LOCK_NL 0 /* null */
46 * either return -EAGAIN from the dlm_lock call or will return 0 from
140 #define DLM_LKF_NOQUEUE 0x00000001
141 #define DLM_LKF_CANCEL 0x00000002
142 #define DLM_LKF_CONVERT 0x00000004
143 #define DLM_LKF_VALBLK 0x00000008
144 #define DLM_LKF_QUECVT 0x00000010
145 #define DLM_LKF_IVVALBLK 0x00000020
146 #define DLM_LKF_CONVDEADLK 0x00000040
147 #define DLM_LKF_PERSISTENT 0x00000080
[all …]
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| /openbmc/linux/lib/ |
| H A D | test_string.c | 16 for (i = 0; i < 256; i++) { in memset16_selftest()
17 for (j = 0; j < 256; j++) { in memset16_selftest()
18 memset(p, 0xa1, 256 * 2 * sizeof(v)); in memset16_selftest()
19 memset16(p + i, 0xb1b2, j); in memset16_selftest()
20 for (k = 0; k < 512; k++) { in memset16_selftest()
23 if (v != 0xa1a1) in memset16_selftest()
26 if (v != 0xb1b2) in memset16_selftest()
29 if (v != 0xa1a1) in memset16_selftest()
39 return (i << 24) | (j << 16) | k | 0x8000; in memset16_selftest()
40 return 0; in memset16_selftest()
[all …]
|
| /openbmc/linux/arch/x86/kvm/ |
| H A D | pmu.h | 15 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
17 #define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000
18 #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001
19 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002
48 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is in kvm_pmu_has_perf_global_ctrl()
156 pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3; in pmc_speculative_in_use()
194 memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap)); in kvm_init_pmu_capability()
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | other.json | 4 "EventCode": "0x28",
6 …s where the core was running with power-delivery for baseline license level 0. This includes non-…
8 "UMask": "0x7"
12 "EventCode": "0x28",
16 "UMask": "0x18"
20 "EventCode": "0x28",
24 "UMask": "0x20"
28 "EventCode": "0xB7, 0xBB",
30 "MSRIndex": "0x1a6,0x1a7",
31 "MSRValue": "0x10004",
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | other.json | 4 "EventCode": "0x28",
6 …s where the core was running with power-delivery for baseline license level 0. This includes non-…
8 "UMask": "0x7"
12 "EventCode": "0x28",
16 "UMask": "0x18"
20 "EventCode": "0x28",
24 "UMask": "0x20"
28 "EventCode": "0xB7, 0xBB",
30 "MSRIndex": "0x1a6,0x1a7",
31 "MSRValue": "0x10004",
[all …]
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| /openbmc/qemu/include/exec/ |
| H A D | cpu-common.h | 19 #define EXCP_INTERRUPT 0x10000 /* async interruption */
20 #define EXCP_HLT 0x10001 /* hlt instruction reached */
21 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
22 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
23 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
24 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
121 * The address space added with @asidx 0 is the one used for the
124 * for defining what semantics address space 0, 1, 2, etc have.
181 /* Returns: 0 on success, -1 on error */
278 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); in cpu_mmu_index()
|
| /openbmc/u-boot/doc/ |
| H A D | README.unaligned-memory-access.txt | 17 from an address that is not evenly divisible by N (i.e. addr % N != 0).
18 For example, reading 4 bytes of data from address 0x10004 is fine, but
19 reading 4 bytes of data from address 0x10005 would be an unaligned memory
35 divisible by N, i.e. addr % N == 0.
88 starting at address 0x10000. With a basic level of understanding, it would
91 structure, i.e. address 0x10002, but that address is not evenly divisible
153 return fold == 0;
157 return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;
163 able to access memory on arbitrary boundaries, the reference to a[0] causes
166 Think about what would happen if addr1 was an odd address such as 0x10003.
|
| /openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | sdio.h | 13 #define SDIOD_FBR_SIZE 0x100
16 #define SDIO_FUNC_ENABLE_1 0x02
17 #define SDIO_FUNC_ENABLE_2 0x04
20 #define SDIO_FUNC_READY_1 0x02
21 #define SDIO_FUNC_READY_2 0x04
24 #define INTR_STATUS_FUNC1 0x2
25 #define INTR_STATUS_FUNC2 0x4
28 #define REG_F0_REG_MASK 0x7FF
29 #define REG_F1_MISC_MASK 0x1FFFF
31 /* function 0 vendor specific CCCR registers */
[all …]
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| /openbmc/linux/Documentation/core-api/ |
| H A D | unaligned-memory-access.rst | 23 from an address that is not evenly divisible by N (i.e. addr % N != 0).
24 For example, reading 4 bytes of data from address 0x10004 is fine, but
25 reading 4 bytes of data from address 0x10005 would be an unaligned memory
41 divisible by N, i.e. addr % N == 0.
94 starting at address 0x10000. With a basic level of understanding, it would
97 structure, i.e. address 0x10002, but that address is not evenly divisible
159 return fold == 0;
163 return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;
169 able to access memory on arbitrary boundaries, the reference to a[0] causes
172 Think about what would happen if addr1 was an odd address such as 0x10003.
[all …]
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| /openbmc/u-boot/drivers/ram/mediatek/ |
| H A D | ddr3-mt7629.c | 17 #define EMI_CONA 0x000
18 #define EMI_CONF 0x028
19 #define EMI_CONM 0x060
22 #define DDRPHY_PLL1 0x0000
23 #define DDRPHY_PLL2 0x0004
24 #define DDRPHY_PLL3 0x0008
25 #define DDRPHY_PLL4 0x000c
26 #define DDRPHY_PLL5 0x0010
27 #define DDRPHY_PLL7 0x0018
28 #define DDRPHY_B0_DLL_ARPI0 0x0080
[all …]
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| /openbmc/linux/include/linux/ |
| H A D | arm-smccc.h | 20 #define ARM_SMCCC_STD_CALL _AC(0,U)
24 #define ARM_SMCCC_SMC_32 0
28 #define ARM_SMCCC_OWNER_MASK 0x3F
31 #define ARM_SMCCC_FUNC_MASK 0xFFFF
47 #define ARM_SMCCC_OWNER_ARCH 0
59 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
61 #define ARM_SMCCC_QUIRK_NONE 0
64 #define ARM_SMCCC_VERSION_1_0 0x10000
65 #define ARM_SMCCC_VERSION_1_1 0x10001
66 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | other.json | 6 "EventCode": "0x63",
12 "EventCode": "0x63",
16 "UMask": "0x2"
21 "EventCode": "0x63",
24 "UMask": "0x2"
29 "EventCode": "0x63",
32 "UMask": "0x1"
36 "EventCode": "0x63",
40 "UMask": "0x1"
45 "EventCode": "0x63",
[all …]
|