1*7e74ece3SIan Rogers[ 2*7e74ece3SIan Rogers { 3*7e74ece3SIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4*7e74ece3SIan Rogers "EventCode": "0x28", 5*7e74ece3SIan Rogers "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 6*7e74ece3SIan Rogers "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 7*7e74ece3SIan Rogers "SampleAfterValue": "200003", 8*7e74ece3SIan Rogers "UMask": "0x7" 9*7e74ece3SIan Rogers }, 10*7e74ece3SIan Rogers { 11*7e74ece3SIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 12*7e74ece3SIan Rogers "EventCode": "0x28", 13*7e74ece3SIan Rogers "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 14*7e74ece3SIan Rogers "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 15*7e74ece3SIan Rogers "SampleAfterValue": "200003", 16*7e74ece3SIan Rogers "UMask": "0x18" 17*7e74ece3SIan Rogers }, 18*7e74ece3SIan Rogers { 19*7e74ece3SIan Rogers "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 20*7e74ece3SIan Rogers "EventCode": "0x28", 21*7e74ece3SIan Rogers "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 22*7e74ece3SIan Rogers "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 23*7e74ece3SIan Rogers "SampleAfterValue": "200003", 24*7e74ece3SIan Rogers "UMask": "0x20" 25*7e74ece3SIan Rogers }, 26*7e74ece3SIan Rogers { 27*7e74ece3SIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 28*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 29*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 30*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 31*7e74ece3SIan Rogers "MSRValue": "0x10004", 32*7e74ece3SIan Rogers "SampleAfterValue": "100003", 33*7e74ece3SIan Rogers "UMask": "0x1" 34*7e74ece3SIan Rogers }, 35*7e74ece3SIan Rogers { 36*7e74ece3SIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 37*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 38*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_CODE_RD.DRAM", 39*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 40*7e74ece3SIan Rogers "MSRValue": "0x184000004", 41*7e74ece3SIan Rogers "SampleAfterValue": "100003", 42*7e74ece3SIan Rogers "UMask": "0x1" 43*7e74ece3SIan Rogers }, 44*7e74ece3SIan Rogers { 45*7e74ece3SIan Rogers "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 46*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 47*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 48*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 49*7e74ece3SIan Rogers "MSRValue": "0x184000004", 50*7e74ece3SIan Rogers "SampleAfterValue": "100003", 51*7e74ece3SIan Rogers "UMask": "0x1" 52*7e74ece3SIan Rogers }, 53*7e74ece3SIan Rogers { 54*7e74ece3SIan Rogers "BriefDescription": "Counts demand data reads that have any type of response.", 55*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 56*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 57*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 58*7e74ece3SIan Rogers "MSRValue": "0x10001", 59*7e74ece3SIan Rogers "SampleAfterValue": "100003", 60*7e74ece3SIan Rogers "UMask": "0x1" 61*7e74ece3SIan Rogers }, 62*7e74ece3SIan Rogers { 63*7e74ece3SIan Rogers "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 64*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 65*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.DRAM", 66*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 67*7e74ece3SIan Rogers "MSRValue": "0x184000001", 68*7e74ece3SIan Rogers "SampleAfterValue": "100003", 69*7e74ece3SIan Rogers "UMask": "0x1" 70*7e74ece3SIan Rogers }, 71*7e74ece3SIan Rogers { 72*7e74ece3SIan Rogers "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 73*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 74*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 75*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 76*7e74ece3SIan Rogers "MSRValue": "0x184000001", 77*7e74ece3SIan Rogers "SampleAfterValue": "100003", 78*7e74ece3SIan Rogers "UMask": "0x1" 79*7e74ece3SIan Rogers }, 80*7e74ece3SIan Rogers { 81*7e74ece3SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 82*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 83*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 84*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 85*7e74ece3SIan Rogers "MSRValue": "0x10002", 86*7e74ece3SIan Rogers "SampleAfterValue": "100003", 87*7e74ece3SIan Rogers "UMask": "0x1" 88*7e74ece3SIan Rogers }, 89*7e74ece3SIan Rogers { 90*7e74ece3SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 91*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 92*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_RFO.DRAM", 93*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 94*7e74ece3SIan Rogers "MSRValue": "0x184000002", 95*7e74ece3SIan Rogers "SampleAfterValue": "100003", 96*7e74ece3SIan Rogers "UMask": "0x1" 97*7e74ece3SIan Rogers }, 98*7e74ece3SIan Rogers { 99*7e74ece3SIan Rogers "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 100*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 101*7e74ece3SIan Rogers "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 102*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 103*7e74ece3SIan Rogers "MSRValue": "0x184000002", 104*7e74ece3SIan Rogers "SampleAfterValue": "100003", 105*7e74ece3SIan Rogers "UMask": "0x1" 106*7e74ece3SIan Rogers }, 107*7e74ece3SIan Rogers { 108*7e74ece3SIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", 109*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 110*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", 111*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 112*7e74ece3SIan Rogers "MSRValue": "0x10400", 113*7e74ece3SIan Rogers "SampleAfterValue": "100003", 114*7e74ece3SIan Rogers "UMask": "0x1" 115*7e74ece3SIan Rogers }, 116*7e74ece3SIan Rogers { 117*7e74ece3SIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 118*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 119*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 120*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 121*7e74ece3SIan Rogers "MSRValue": "0x184000400", 122*7e74ece3SIan Rogers "SampleAfterValue": "100003", 123*7e74ece3SIan Rogers "UMask": "0x1" 124*7e74ece3SIan Rogers }, 125*7e74ece3SIan Rogers { 126*7e74ece3SIan Rogers "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 127*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 128*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 129*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 130*7e74ece3SIan Rogers "MSRValue": "0x184000400", 131*7e74ece3SIan Rogers "SampleAfterValue": "100003", 132*7e74ece3SIan Rogers "UMask": "0x1" 133*7e74ece3SIan Rogers }, 134*7e74ece3SIan Rogers { 135*7e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", 136*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 137*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", 138*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 139*7e74ece3SIan Rogers "MSRValue": "0x10010", 140*7e74ece3SIan Rogers "SampleAfterValue": "100003", 141*7e74ece3SIan Rogers "UMask": "0x1" 142*7e74ece3SIan Rogers }, 143*7e74ece3SIan Rogers { 144*7e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 145*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 146*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", 147*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 148*7e74ece3SIan Rogers "MSRValue": "0x184000010", 149*7e74ece3SIan Rogers "SampleAfterValue": "100003", 150*7e74ece3SIan Rogers "UMask": "0x1" 151*7e74ece3SIan Rogers }, 152*7e74ece3SIan Rogers { 153*7e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 154*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 155*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", 156*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 157*7e74ece3SIan Rogers "MSRValue": "0x184000010", 158*7e74ece3SIan Rogers "SampleAfterValue": "100003", 159*7e74ece3SIan Rogers "UMask": "0x1" 160*7e74ece3SIan Rogers }, 161*7e74ece3SIan Rogers { 162*7e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", 163*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 164*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", 165*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 166*7e74ece3SIan Rogers "MSRValue": "0x10020", 167*7e74ece3SIan Rogers "SampleAfterValue": "100003", 168*7e74ece3SIan Rogers "UMask": "0x1" 169*7e74ece3SIan Rogers }, 170*7e74ece3SIan Rogers { 171*7e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 172*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 173*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_RFO.DRAM", 174*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 175*7e74ece3SIan Rogers "MSRValue": "0x184000020", 176*7e74ece3SIan Rogers "SampleAfterValue": "100003", 177*7e74ece3SIan Rogers "UMask": "0x1" 178*7e74ece3SIan Rogers }, 179*7e74ece3SIan Rogers { 180*7e74ece3SIan Rogers "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 181*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 182*7e74ece3SIan Rogers "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", 183*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 184*7e74ece3SIan Rogers "MSRValue": "0x184000020", 185*7e74ece3SIan Rogers "SampleAfterValue": "100003", 186*7e74ece3SIan Rogers "UMask": "0x1" 187*7e74ece3SIan Rogers }, 188*7e74ece3SIan Rogers { 189*7e74ece3SIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 190*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 191*7e74ece3SIan Rogers "EventName": "OCR.OTHER.ANY_RESPONSE", 192*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 193*7e74ece3SIan Rogers "MSRValue": "0x18000", 194*7e74ece3SIan Rogers "SampleAfterValue": "100003", 195*7e74ece3SIan Rogers "UMask": "0x1" 196*7e74ece3SIan Rogers }, 197*7e74ece3SIan Rogers { 198*7e74ece3SIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 199*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 200*7e74ece3SIan Rogers "EventName": "OCR.OTHER.DRAM", 201*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 202*7e74ece3SIan Rogers "MSRValue": "0x184008000", 203*7e74ece3SIan Rogers "SampleAfterValue": "100003", 204*7e74ece3SIan Rogers "UMask": "0x1" 205*7e74ece3SIan Rogers }, 206*7e74ece3SIan Rogers { 207*7e74ece3SIan Rogers "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 208*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 209*7e74ece3SIan Rogers "EventName": "OCR.OTHER.LOCAL_DRAM", 210*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 211*7e74ece3SIan Rogers "MSRValue": "0x184008000", 212*7e74ece3SIan Rogers "SampleAfterValue": "100003", 213*7e74ece3SIan Rogers "UMask": "0x1" 214*7e74ece3SIan Rogers }, 215*7e74ece3SIan Rogers { 216*7e74ece3SIan Rogers "BriefDescription": "Counts streaming stores that have any type of response.", 217*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 218*7e74ece3SIan Rogers "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 219*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 220*7e74ece3SIan Rogers "MSRValue": "0x10800", 221*7e74ece3SIan Rogers "SampleAfterValue": "100003", 222*7e74ece3SIan Rogers "UMask": "0x1" 223*7e74ece3SIan Rogers }, 224*7e74ece3SIan Rogers { 225*7e74ece3SIan Rogers "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 226*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 227*7e74ece3SIan Rogers "EventName": "OCR.STREAMING_WR.DRAM", 228*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 229*7e74ece3SIan Rogers "MSRValue": "0x184000800", 230*7e74ece3SIan Rogers "SampleAfterValue": "100003", 231*7e74ece3SIan Rogers "UMask": "0x1" 232*7e74ece3SIan Rogers }, 233*7e74ece3SIan Rogers { 234*7e74ece3SIan Rogers "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 235*7e74ece3SIan Rogers "EventCode": "0xB7, 0xBB", 236*7e74ece3SIan Rogers "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", 237*7e74ece3SIan Rogers "MSRIndex": "0x1a6,0x1a7", 238*7e74ece3SIan Rogers "MSRValue": "0x184000800", 239*7e74ece3SIan Rogers "SampleAfterValue": "100003", 240*7e74ece3SIan Rogers "UMask": "0x1" 241*7e74ece3SIan Rogers } 242*7e74ece3SIan Rogers] 243