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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,bcm63xx-spi.yaml64 reg = <0x10000800 0x70c>;
70 #size-cells = <0>;
/openbmc/u-boot/doc/device-tree-bindings/leds/
H A Dleds-bcm6328.txt16 - #size-cells : must be 0.
34 - reg : LED pin number (only LEDs 0 to 23 are valid).
46 #size-cells = <0>;
47 reg = <0x10000800 0x24>;
70 #size-cells = <0>;
71 reg = <0x10001900 0x24>;
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6368.dtsi20 reg = <0x10000000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
62 reg = <0x18000000 0x2000000>;
78 reg = <0x10000008 0x4>;
84 offset = <0x0>;
85 mask = <0x1>;
[all …]
H A Dbrcm,bcm6328.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
62 reg = <0x10000004 0x4>;
75 reg = <0x10000010 0x4>;
81 reg = <0x10000068 0x4>;
87 offset = <0x0>;
[all …]
H A Dbrcm,bcm6362.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
76 reg = <0x10000008 0x4>;
82 offset = <0x0>;
83 mask = <0x1>;
[all …]
H A Dbrcm,bcm63268.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
69 reg = <0x100000ac 0x4>;
82 reg = <0x10000008 0x4>;
88 offset = <0x0>;
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm6362.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
H A Dbcm6368.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
48 #address-cells = <0>;
64 reg = <0x10000004 0x4>;
70 reg = <0x10000008 0x4>;
75 offset = <0x0>;
76 mask = <0x1>;
82 reg = <0x10000010 0x4>;
[all …]
H A Dbcm6328.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
55 #address-cells = <0>;
71 reg = <0x10000004 0x4>;
77 reg = <0x10000010 0x4>;
83 reg = <0x10000020 0x10>,
84 <0x10000030 0x10>;
[all …]
H A Dbcm63268.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dleds-bcm6328.yaml26 with 0 meaning hardware control enabled and 1 hardware control disabled. This
67 const: 0
79 description: LED pin number (only LEDs 0 to 23 are valid).
95 signals can get muxed into these LEDs. Only valid for LEDs 0 to 7,
96 where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and signals 4 to
106 hardware signals can get muxed into these LEDs. Only valid for LEDs 0
107 to 7, where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and
129 #size-cells = <0>;
130 reg = <0x10000800 0x24>;
176 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
H A Dgk208.fuc5.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
/openbmc/qemu/hw/ssi/
H A Daspeed_smc.c41 #define R_CONF (0x00 / 4)
52 #define CONF_FLASH_TYPE0 0
53 #define CONF_FLASH_TYPE_NOR 0x0
54 #define CONF_FLASH_TYPE_NAND 0x1
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
58 #define R_CE_CTRL (0x04 / 4)
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
66 #define R_INTR_CTRL (0x08 / 4)
75 #define R_CE_CMD_CTRL (0x0C / 4)
77 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c61 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 mmDB_DEBUG, 0xffffffff, 0x00000000,
64 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 0x340c, 0x000000c0, 0x00800040,
68 0x360c, 0x000000c0, 0x00800040,
69 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsi.c161 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
162 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
163 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
167 (0x8000 << 16) | (0x98f4 >> 2),
168 0x00000000,
169 (0x8040 << 16) | (0x98f4 >> 2),
170 0x00000000,
171 (0x8000 << 16) | (0xe80 >> 2),
172 0x00000000,
173 (0x8040 << 16) | (0xe80 >> 2),
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]