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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dst,stm32-qspi.yaml65 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
68 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
69 <&mdma1 22 0x10 0x100008 0x0 0x0>;
75 #size-cells = <0>;
77 flash@0 {
79 reg = <0>;
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5271.h21 #define MCF_FMPLL_SYNCR 0x120000
22 #define MCF_FMPLL_SYNSR 0x120004
24 #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
25 #define MCF_SYNCR_MFD_4X 0x00000000
26 #define MCF_SYNCR_MFD_6X 0x01000000
27 #define MCF_SYNCR_MFD_8X 0x02000000
28 #define MCF_SYNCR_MFD_10X 0x03000000
29 #define MCF_SYNCR_MFD_12X 0x04000000
30 #define MCF_SYNCR_MFD_14X 0x05000000
31 #define MCF_SYNCR_MFD_16X 0x06000000
[all …]
H A Dm5282.h14 #define PLL_SYNCR_LOLRE (0x8000)
15 #define PLL_SYNCR_MFD2 (0x4000)
16 #define PLL_SYNCR_MFD1 (0x2000)
17 #define PLL_SYNCR_MFD0 (0x1000)
18 #define PLL_SYNCR_LOCRE (0x0800)
19 #define PLL_SYNCR_RFC2 (0x0400)
20 #define PLL_SYNCR_RFC1 (0x0200)
21 #define PLL_SYNCR_RFC0 (0x0100)
22 #define PLL_SYNCR_LOCEN (0x0080)
23 #define PLL_SYNCR_DISCLK (0x0040)
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm523xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
H A Dm527xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/openbmc/linux/sound/pci/hda/
H A Dpatch_realtek.c164 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_read_coefex_idx()
165 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); in __alc_read_coefex_idx()
181 alc_read_coefex_idx(codec, 0x20, coef_idx)
186 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_write_coefex_idx()
187 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PROC_COEF, coef_val); in __alc_write_coefex_idx()
199 alc_write_coefex_idx(codec, 0x20, coef_idx, coef_val)
222 alc_update_coefex_idx(codec, 0x20, coef_idx, mask, bits_set)
224 /* a special bypass for COEF 0; read the cached value at the second time */
230 spec->coef0 = alc_read_coef_idx(codec, 0); in alc_get_coef0()
[all...]
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "MMID", 89, 0 },
36 { "DDR", 104, 0 },
37 { "176", 176, 0 },
38 { "208", 208, 0 },
39 { "INTERRUPT", 226, 0 },
40 { "INTCLEAR", 227, 0 },
[all …]