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/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/openbmc/linux/sound/soc/qcom/
H A Dlpass-sc7280.c114 int chan = 0; in sc7280_lpass_alloc_dma_channel()
193 return 0; in sc7280_lpass_free_dma_channel()
210 for (i = 0; i < drvdata->num_clks; i++) in sc7280_lpass_init()
225 return 0; in sc7280_lpass_init()
233 return 0; in sc7280_lpass_exit()
248 return 0; in sc7280_lpass_dev_suspend()
256 .i2sctrl_reg_base = 0x1000,
257 .i2sctrl_reg_stride = 0x1000,
259 .irq_reg_base = 0x9000,
260 .irq_reg_stride = 0x1000,
[all …]
H A Dlpass-sc7180.c80 int chan = 0; in sc7180_lpass_alloc_dma_channel()
120 return 0; in sc7180_lpass_free_dma_channel()
137 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
152 return 0; in sc7180_lpass_init()
160 return 0; in sc7180_lpass_exit()
175 return 0; in sc7180_lpass_dev_suspend()
183 .i2sctrl_reg_base = 0x1000,
184 .i2sctrl_reg_stride = 0x1000,
186 .irq_reg_base = 0x9000,
187 .irq_reg_stride = 0x1000,
[all …]
H A Dlpass-apq8016.c127 int chan = 0; in apq8016_lpass_alloc_dma_channel()
154 return 0; in apq8016_lpass_free_dma_channel()
171 for (i = 0; i < drvdata->num_clks; i++) in apq8016_lpass_init()
208 return 0; in apq8016_lpass_init()
222 return 0; in apq8016_lpass_exit()
227 .i2sctrl_reg_base = 0x1000,
228 .i2sctrl_reg_stride = 0x1000,
230 .irq_reg_base = 0x6000,
231 .irq_reg_stride = 0x1000,
233 .rdma_reg_base = 0x8400,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h174 #define MM_TOP_RSVD 0xa0000000U
175 #define MM_TOP_RSVD_SIZE 0x4000000
176 #define MM_GIC_APU_DIST_MAIN 0xf9000000U
177 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
178 #define MM_GIC_APU_REDIST_0 0xf9080000U
179 #define MM_GIC_APU_REDIST_0_SIZE 0x80000
181 #define MM_UART0 0xff000000U
182 #define MM_UART0_SIZE 0x10000
183 #define MM_UART1 0xff010000U
184 #define MM_UART1_SIZE 0x10000
[all …]
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D05827 seq=`basename $0`
48 trap "_cleanup; exit \$status" 0 1 2 3 15
62 _unsupported_imgopts 'refcount_bits=1[^0-9]' data_file
74 $QEMU_IO -c 'write -P 0xa 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
75 $QEMU_IO -c 'write -P 0xb 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c 'write -P 0xc 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
78 $QEMU_IO -c 'write -P 0xd 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
83 $QEMU_IO -c 'read -P 0xc 0x1000 0x1000' "$TEST_IMG" | _filter_qemu_io
84 $QEMU_IO -c 'read -P 0xd 0x2000 0x1000' "$TEST_IMG" | _filter_qemu_io
90 $QEMU_IO_NBD -r -c 'read -P 0xa 0x1000 0x1000' "$nbd_snapshot_img" | _filter_qemu_io
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
H A Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
9 compatible = "ingenic,x1000", "ingenic,x1000e";
13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
34 reg = <0x10001000 0x50>;
[all …]
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhisi-x5hd2.dtsi20 #address-cells = <0>;
23 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
31 ranges = <0 0xf8000000 0x8000000>;
41 reg = <0x00002000 0x1000>;
43 interrupts = <0 24 4>;
55 reg = <0x00a29000 0x1000>;
57 interrupts = <0 25 4>;
64 reg = <0x00a2a000 0x1000>;
66 interrupts = <0 26 4>;
73 reg = <0x00a2b000 0x1000>;
[all …]
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc25 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0)
26 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0)
27 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0)
29 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0)
30 XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0)
31 XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0)
32 XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0)
33 XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0)
34 XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0)
[all …]
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc22 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
23 0, 0, 0, 0, 0, 0)
24 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
25 0, 0, 0, 0, 0, 0)
26 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
27 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
29 0, 0, 0, 0, 0, 0)
30 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3,
31 0, 0, 0, 0, 0, 0)
[all …]
/openbmc/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
22 bootrom: bootrom@0 {
23 reg = <0x00000000 0x80000>;
28 reg = <0xa4000000 0x20000>; /* 128k */
31 ranges = <0 0xa4000000 0x20000>;
33 sram@0 {
34 reg = <0x0 0x20000>;
39 #clock-cells = <0>;
[all …]
/openbmc/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
[all …]
/openbmc/linux/arch/arm64/boot/dts/lg/
H A Dlg1312.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
H A Dlg1313.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
[all …]
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]

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