Lines Matching +full:0 +full:x1000
84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
94 #define FSL_IMX6_OPENVG_ADDR 0x02204000
95 #define FSL_IMX6_OPENVG_SIZE 0x4000
96 #define FSL_IMX6_SATA_ADDR 0x02200000
97 #define FSL_IMX6_SATA_SIZE 0x4000
98 #define FSL_IMX6_AIPS_2_ADDR 0x02100000
99 #define FSL_IMX6_AIPS_2_SIZE 0x100000
101 #define FSL_IMX6_UART5_ADDR 0x021F4000
102 #define FSL_IMX6_UART5_SIZE 0x4000
103 #define FSL_IMX6_UART4_ADDR 0x021F0000
104 #define FSL_IMX6_UART4_SIZE 0x4000
105 #define FSL_IMX6_UART3_ADDR 0x021EC000
106 #define FSL_IMX6_UART3_SIZE 0x4000
107 #define FSL_IMX6_UART2_ADDR 0x021E8000
108 #define FSL_IMX6_UART2_SIZE 0x4000
109 #define FSL_IMX6_VDOA_ADDR 0x021E4000
110 #define FSL_IMX6_VDOA_SIZE 0x4000
111 #define FSL_IMX6_MIPI_DSI_ADDR 0x021E0000
112 #define FSL_IMX6_MIPI_DSI_SIZE 0x4000
113 #define FSL_IMX6_MIPI_CSI_ADDR 0x021DC000
114 #define FSL_IMX6_MIPI_CSI_SIZE 0x4000
115 #define FSL_IMX6_AUDMUX_ADDR 0x021D8000
116 #define FSL_IMX6_AUDMUX_SIZE 0x4000
117 #define FSL_IMX6_TZASC2_ADDR 0x021D4000
118 #define FSL_IMX6_TZASC2_SIZE 0x4000
119 #define FSL_IMX6_TZASC1_ADDR 0x021D0000
120 #define FSL_IMX6_TZASC1_SIZE 0x4000
121 #define FSL_IMX6_CSU_ADDR 0x021C0000
122 #define FSL_IMX6_CSU_SIZE 0x4000
123 #define FSL_IMX6_OCOTPCTRL_ADDR 0x021BC000
124 #define FSL_IMX6_OCOTPCTRL_SIZE 0x4000
125 #define FSL_IMX6_EIM_ADDR 0x021B8000
126 #define FSL_IMX6_EIM_SIZE 0x4000
127 #define FSL_IMX6_MMDC1_ADDR 0x021B4000
128 #define FSL_IMX6_MMDC1_SIZE 0x4000
129 #define FSL_IMX6_MMDC0_ADDR 0x021B0000
130 #define FSL_IMX6_MMDC0_SIZE 0x4000
131 #define FSL_IMX6_ROMCP_ADDR 0x021AC000
132 #define FSL_IMX6_ROMCP_SIZE 0x4000
133 #define FSL_IMX6_I2C3_ADDR 0x021A8000
134 #define FSL_IMX6_I2C3_SIZE 0x4000
135 #define FSL_IMX6_I2C2_ADDR 0x021A4000
136 #define FSL_IMX6_I2C2_SIZE 0x4000
137 #define FSL_IMX6_I2C1_ADDR 0x021A0000
138 #define FSL_IMX6_I2C1_SIZE 0x4000
139 #define FSL_IMX6_uSDHC4_ADDR 0x0219C000
140 #define FSL_IMX6_uSDHC4_SIZE 0x4000
141 #define FSL_IMX6_uSDHC3_ADDR 0x02198000
142 #define FSL_IMX6_uSDHC3_SIZE 0x4000
143 #define FSL_IMX6_uSDHC2_ADDR 0x02194000
144 #define FSL_IMX6_uSDHC2_SIZE 0x4000
145 #define FSL_IMX6_uSDHC1_ADDR 0x02190000
146 #define FSL_IMX6_uSDHC1_SIZE 0x4000
147 #define FSL_IMX6_MLB150_ADDR 0x0218C000
148 #define FSL_IMX6_MLB150_SIZE 0x4000
149 #define FSL_IMX6_ENET_ADDR 0x02188000
150 #define FSL_IMX6_ENET_SIZE 0x4000
151 #define FSL_IMX6_USBOH3_USB_ADDR 0x02184000
152 #define FSL_IMX6_USBOH3_USB_SIZE 0x4000
153 #define FSL_IMX6_AIPS2_CFG_ADDR 0x0217C000
154 #define FSL_IMX6_AIPS2_CFG_SIZE 0x4000
156 #define FSL_IMX6_PTF_CTRL_ADDR 0x02160000
157 #define FSL_IMX6_PTF_CTRL_SIZE 0x1000
158 #define FSL_IMX6_PTM3_ADDR 0x0215F000
159 #define FSL_IMX6_PTM3_SIZE 0x1000
160 #define FSL_IMX6_PTM2_ADDR 0x0215E000
161 #define FSL_IMX6_PTM2_SIZE 0x1000
162 #define FSL_IMX6_PTM1_ADDR 0x0215D000
163 #define FSL_IMX6_PTM1_SIZE 0x1000
164 #define FSL_IMX6_PTM0_ADDR 0x0215C000
165 #define FSL_IMX6_PTM0_SIZE 0x1000
166 #define FSL_IMX6_CTI3_ADDR 0x0215B000
167 #define FSL_IMX6_CTI3_SIZE 0x1000
168 #define FSL_IMX6_CTI2_ADDR 0x0215A000
169 #define FSL_IMX6_CTI2_SIZE 0x1000
170 #define FSL_IMX6_CTI1_ADDR 0x02159000
171 #define FSL_IMX6_CTI1_SIZE 0x1000
172 #define FSL_IMX6_CTI0_ADDR 0x02158000
173 #define FSL_IMX6_CTI0_SIZE 0x1000
174 #define FSL_IMX6_CPU3_PMU_ADDR 0x02157000
175 #define FSL_IMX6_CPU3_PMU_SIZE 0x1000
176 #define FSL_IMX6_CPU3_DEBUG_IF_ADDR 0x02156000
177 #define FSL_IMX6_CPU3_DEBUG_IF_SIZE 0x1000
178 #define FSL_IMX6_CPU2_PMU_ADDR 0x02155000
179 #define FSL_IMX6_CPU2_PMU_SIZE 0x1000
180 #define FSL_IMX6_CPU2_DEBUG_IF_ADDR 0x02154000
181 #define FSL_IMX6_CPU2_DEBUG_IF_SIZE 0x1000
182 #define FSL_IMX6_CPU1_PMU_ADDR 0x02153000
183 #define FSL_IMX6_CPU1_PMU_SIZE 0x1000
184 #define FSL_IMX6_CPU1_DEBUG_IF_ADDR 0x02152000
185 #define FSL_IMX6_CPU1_DEBUG_IF_SIZE 0x1000
186 #define FSL_IMX6_CPU0_PMU_ADDR 0x02151000
187 #define FSL_IMX6_CPU0_PMU_SIZE 0x1000
188 #define FSL_IMX6_CPU0_DEBUG_IF_ADDR 0x02150000
189 #define FSL_IMX6_CPU0_DEBUG_IF_SIZE 0x1000
190 #define FSL_IMX6_CA9_INTEG_ADDR 0x0214F000
191 #define FSL_IMX6_CA9_INTEG_SIZE 0x1000
192 #define FSL_IMX6_FUNNEL_ADDR 0x02144000
193 #define FSL_IMX6_FUNNEL_SIZE 0x1000
194 #define FSL_IMX6_TPIU_ADDR 0x02143000
195 #define FSL_IMX6_TPIU_SIZE 0x1000
196 #define FSL_IMX6_EXT_CTI_ADDR 0x02142000
197 #define FSL_IMX6_EXT_CTI_SIZE 0x1000
198 #define FSL_IMX6_ETB_ADDR 0x02141000
199 #define FSL_IMX6_ETB_SIZE 0x1000
200 #define FSL_IMX6_DAP_ROM_TABLE_ADDR 0x02140000
201 #define FSL_IMX6_DAP_ROM_TABLE_SIZE 0x1000
203 #define FSL_IMX6_CAAM_ADDR 0x02100000
204 #define FSL_IMX6_CAAM_SIZE 0x10000
206 #define FSL_IMX6_AIPS_1_ADDR 0x02000000
207 #define FSL_IMX6_AIPS_1_SIZE 0x100000
209 #define FSL_IMX6_SDMA_ADDR 0x020EC000
210 #define FSL_IMX6_SDMA_SIZE 0x4000
211 #define FSL_IMX6_DCIC2_ADDR 0x020E8000
212 #define FSL_IMX6_DCIC2_SIZE 0x4000
213 #define FSL_IMX6_DCIC1_ADDR 0x020E4000
214 #define FSL_IMX6_DCIC1_SIZE 0x4000
215 #define FSL_IMX6_IOMUXC_ADDR 0x020E0000
216 #define FSL_IMX6_IOMUXC_SIZE 0x4000
217 #define FSL_IMX6_PGCARM_ADDR 0x020DCA00
218 #define FSL_IMX6_PGCARM_SIZE 0x20
219 #define FSL_IMX6_PGCPU_ADDR 0x020DC260
220 #define FSL_IMX6_PGCPU_SIZE 0x20
221 #define FSL_IMX6_GPC_ADDR 0x020DC000
222 #define FSL_IMX6_GPC_SIZE 0x4000
223 #define FSL_IMX6_SRC_ADDR 0x020D8000
224 #define FSL_IMX6_SRC_SIZE 0x4000
225 #define FSL_IMX6_EPIT2_ADDR 0x020D4000
226 #define FSL_IMX6_EPIT2_SIZE 0x4000
227 #define FSL_IMX6_EPIT1_ADDR 0x020D0000
228 #define FSL_IMX6_EPIT1_SIZE 0x4000
229 #define FSL_IMX6_SNVSHP_ADDR 0x020CC000
230 #define FSL_IMX6_SNVSHP_SIZE 0x4000
231 #define FSL_IMX6_USBPHY2_ADDR 0x020CA000
232 #define FSL_IMX6_USBPHY2_SIZE 0x1000
233 #define FSL_IMX6_USBPHY1_ADDR 0x020C9000
234 #define FSL_IMX6_USBPHY1_SIZE 0x1000
235 #define FSL_IMX6_ANALOG_ADDR 0x020C8000
236 #define FSL_IMX6_ANALOG_SIZE 0x1000
237 #define FSL_IMX6_CCM_ADDR 0x020C4000
238 #define FSL_IMX6_CCM_SIZE 0x4000
239 #define FSL_IMX6_WDOG2_ADDR 0x020C0000
240 #define FSL_IMX6_WDOG2_SIZE 0x4000
241 #define FSL_IMX6_WDOG1_ADDR 0x020BC000
242 #define FSL_IMX6_WDOG1_SIZE 0x4000
243 #define FSL_IMX6_KPP_ADDR 0x020B8000
244 #define FSL_IMX6_KPP_SIZE 0x4000
245 #define FSL_IMX6_GPIO7_ADDR 0x020B4000
246 #define FSL_IMX6_GPIO7_SIZE 0x4000
247 #define FSL_IMX6_GPIO6_ADDR 0x020B0000
248 #define FSL_IMX6_GPIO6_SIZE 0x4000
249 #define FSL_IMX6_GPIO5_ADDR 0x020AC000
250 #define FSL_IMX6_GPIO5_SIZE 0x4000
251 #define FSL_IMX6_GPIO4_ADDR 0x020A8000
252 #define FSL_IMX6_GPIO4_SIZE 0x4000
253 #define FSL_IMX6_GPIO3_ADDR 0x020A4000
254 #define FSL_IMX6_GPIO3_SIZE 0x4000
255 #define FSL_IMX6_GPIO2_ADDR 0x020A0000
256 #define FSL_IMX6_GPIO2_SIZE 0x4000
257 #define FSL_IMX6_GPIO1_ADDR 0x0209C000
258 #define FSL_IMX6_GPIO1_SIZE 0x4000
259 #define FSL_IMX6_GPT_ADDR 0x02098000
260 #define FSL_IMX6_GPT_SIZE 0x4000
261 #define FSL_IMX6_CAN2_ADDR 0x02094000
262 #define FSL_IMX6_CAN2_SIZE 0x4000
263 #define FSL_IMX6_CAN1_ADDR 0x02090000
264 #define FSL_IMX6_CAN1_SIZE 0x4000
265 #define FSL_IMX6_PWM4_ADDR 0x0208C000
266 #define FSL_IMX6_PWM4_SIZE 0x4000
267 #define FSL_IMX6_PWM3_ADDR 0x02088000
268 #define FSL_IMX6_PWM3_SIZE 0x4000
269 #define FSL_IMX6_PWM2_ADDR 0x02084000
270 #define FSL_IMX6_PWM2_SIZE 0x4000
271 #define FSL_IMX6_PWM1_ADDR 0x02080000
272 #define FSL_IMX6_PWM1_SIZE 0x4000
273 #define FSL_IMX6_AIPS1_CFG_ADDR 0x0207C000
274 #define FSL_IMX6_AIPS1_CFG_SIZE 0x4000
275 #define FSL_IMX6_VPU_ADDR 0x02040000
276 #define FSL_IMX6_VPU_SIZE 0x3C000
277 #define FSL_IMX6_AIPS1_SPBA_ADDR 0x0203C000
278 #define FSL_IMX6_AIPS1_SPBA_SIZE 0x4000
279 #define FSL_IMX6_ASRC_ADDR 0x02034000
280 #define FSL_IMX6_ASRC_SIZE 0x4000
281 #define FSL_IMX6_SSI3_ADDR 0x02030000
282 #define FSL_IMX6_SSI3_SIZE 0x4000
283 #define FSL_IMX6_SSI2_ADDR 0x0202C000
284 #define FSL_IMX6_SSI2_SIZE 0x4000
285 #define FSL_IMX6_SSI1_ADDR 0x02028000
286 #define FSL_IMX6_SSI1_SIZE 0x4000
287 #define FSL_IMX6_ESAI_ADDR 0x02024000
288 #define FSL_IMX6_ESAI_SIZE 0x4000
289 #define FSL_IMX6_UART1_ADDR 0x02020000
290 #define FSL_IMX6_UART1_SIZE 0x4000
291 #define FSL_IMX6_eCSPI5_ADDR 0x02018000
292 #define FSL_IMX6_eCSPI5_SIZE 0x4000
293 #define FSL_IMX6_eCSPI4_ADDR 0x02014000
294 #define FSL_IMX6_eCSPI4_SIZE 0x4000
295 #define FSL_IMX6_eCSPI3_ADDR 0x02010000
296 #define FSL_IMX6_eCSPI3_SIZE 0x4000
297 #define FSL_IMX6_eCSPI2_ADDR 0x0200C000
298 #define FSL_IMX6_eCSPI2_SIZE 0x4000
299 #define FSL_IMX6_eCSPI1_ADDR 0x02008000
300 #define FSL_IMX6_eCSPI1_SIZE 0x4000
301 #define FSL_IMX6_SPDIF_ADDR 0x02004000
302 #define FSL_IMX6_SPDIF_SIZE 0x4000
304 #define FSL_IMX6_PCIe_REG_ADDR 0x01FFC000
305 #define FSL_IMX6_PCIe_REG_SIZE 0x4000
306 #define FSL_IMX6_PCIe_ADDR 0x01000000
307 #define FSL_IMX6_PCIe_SIZE 0xFFC000
308 #define FSL_IMX6_GPV_1_PL301_CFG_ADDR 0x00C00000
309 #define FSL_IMX6_GPV_1_PL301_CFG_SIZE 0x100000
310 #define FSL_IMX6_GPV_0_PL301_CFG_ADDR 0x00B00000
311 #define FSL_IMX6_GPV_0_PL301_CFG_SIZE 0x100000
312 #define FSL_IMX6_PL310_ADDR 0x00A02000
313 #define FSL_IMX6_PL310_SIZE 0x1000
314 #define FSL_IMX6_A9MPCORE_ADDR 0x00A00000
315 #define FSL_IMX6_A9MPCORE_SIZE 0x2000
316 #define FSL_IMX6_OCRAM_ALIAS_ADDR 0x00940000
317 #define FSL_IMX6_OCRAM_ALIAS_SIZE 0xC0000
318 #define FSL_IMX6_OCRAM_ADDR 0x00900000
319 #define FSL_IMX6_OCRAM_SIZE 0x40000
320 #define FSL_IMX6_GPV_4_PL301_CFG_ADDR 0x00800000
321 #define FSL_IMX6_GPV_4_PL301_CFG_SIZE 0x100000
322 #define FSL_IMX6_GPV_3_PL301_CFG_ADDR 0x00300000
323 #define FSL_IMX6_GPV_3_PL301_CFG_SIZE 0x100000
324 #define FSL_IMX6_GPV_2_PL301_CFG_ADDR 0x00200000
325 #define FSL_IMX6_GPV_2_PL301_CFG_SIZE 0x100000
326 #define FSL_IMX6_DTCP_ADDR 0x00138000
327 #define FSL_IMX6_DTCP_SIZE 0x4000
328 #define FSL_IMX6_GPU_2D_ADDR 0x00134000
329 #define FSL_IMX6_GPU_2D_SIZE 0x4000
330 #define FSL_IMX6_GPU_3D_ADDR 0x00130000
331 #define FSL_IMX6_GPU_3D_SIZE 0x4000
332 #define FSL_IMX6_HDMI_ADDR 0x00120000
333 #define FSL_IMX6_HDMI_SIZE 0x9000
334 #define FSL_IMX6_BCH_ADDR 0x00114000
335 #define FSL_IMX6_BCH_SIZE 0x4000
336 #define FSL_IMX6_GPMI_ADDR 0x00112000
337 #define FSL_IMX6_GPMI_SIZE 0x2000
338 #define FSL_IMX6_APBH_BRIDGE_DMA_ADDR 0x00110000
339 #define FSL_IMX6_APBH_BRIDGE_DMA_SIZE 0x2000
340 #define FSL_IMX6_CAAM_MEM_ADDR 0x00100000
341 #define FSL_IMX6_CAAM_MEM_SIZE 0x4000
342 #define FSL_IMX6_ROM_ADDR 0x00000000
343 #define FSL_IMX6_ROM_SIZE 0x18000
345 #define FSL_IMX6_IOMUXC_IRQ 0