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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsocionext,uniphier-pcie.yaml88 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
95 bus-range = <0x0 0xff>;
97 ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
98 <0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
104 interrupts = <0 224 4>, <0 225 4>;
105 interrupt-map-mask = <0 0 0 7>;
106 interrupt-map = <0 0 0 1 &pcie_intc 0>,
107 <0 0 0 2 &pcie_intc 1>,
108 <0 0 0 3 &pcie_intc 2>,
109 <0 0 0 4 &pcie_intc 3>;
[all …]
/openbmc/qemu/target/ppc/
H A Dmmu-hash32.h14 #define SR32_T 0x80000000
15 #define SR32_KS 0x40000000
16 #define SR32_KP 0x20000000
17 #define SR32_NX 0x10000000
18 #define SR32_VSID 0x00ffffff
24 #define BATU32_BEPIU 0xf0000000
25 #define BATU32_BEPIL 0x0ffe0000
26 #define BATU32_BEPI 0xfffe0000
27 #define BATU32_BL 0x00001ffc
28 #define BATU32_VS 0x00000002
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100.h21 #define MAC_CONTROL 0x00000000 /* MAC Control */
22 #define MAC_ADDR_HIGH 0x00000004 /* MAC Address High */
23 #define MAC_ADDR_LOW 0x00000008 /* MAC Address Low */
24 #define MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */
25 #define MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */
26 #define MAC_MII_ADDR 0x00000014 /* MII Address */
27 #define MAC_MII_DATA 0x00000018 /* MII Data */
28 #define MAC_FLOW_CTRL 0x0000001c /* Flow Control */
29 #define MAC_VLAN1 0x00000020 /* VLAN1 Tag */
30 #define MAC_VLAN2 0x00000024 /* VLAN2 Tag */
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dimx_rproc.c28 #define IMX7D_SRC_SCR 0x0C
32 #define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
46 #define IMX8M_GPR22 0x58
47 #define IMX8M_GPR22_CM7_CPUWAIT BIT(0)
49 /* Address: 0x020D8000 */
50 #define IMX6SX_SRC_SCR 0x00
66 #define IMX_SIP_RPROC 0xC2000005
67 #define IMX_SIP_RPROC_START 0x00
68 #define IMX_SIP_RPROC_STARTED 0x01
69 #define IMX_SIP_RPROC_STOP 0x02
[all …]
/openbmc/qemu/hw/m68k/
H A Dmcf5206.c33 #define TMR_RST 0x01
34 #define TMR_CLK 0x06
35 #define TMR_FRR 0x08
36 #define TMR_ORI 0x10
37 #define TMR_OM 0x20
38 #define TMR_CE 0xc0
40 #define TER_CAP 0x01
41 #define TER_REF 0x02
45 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) in m5206_timer_update()
53 s->tmr = 0; in m5206_timer_reset()
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_frontend.c27 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
28 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
29 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
30 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
31 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
32 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
33 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
34 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
38 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
39 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
[all …]
/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-ld20.dtsi21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_display.c35 #define PWM_ON 0
39 #define PWM_OFF 0
67 { 720, 576, 50, 37037, 27000, 137, 5, 20, 27, 2, 2, 0, FB_VMODE_INTERLACED },
68 { 720, 480, 60, 37037, 27000, 116, 20, 16, 27, 2, 2, 0, FB_VMODE_INTERLACED },
86 return 0; in await_completion()
128 return 0; in sunxi_hdmi_hpd_detect()
144 clock_set_pll3(0); in sunxi_hdmi_shutdown()
165 return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0); in sunxi_hdmi_ddc_do_command()
174 while (count > 0) { in sunxi_hdmi_ddc_read()
185 for (i = 0; i < n; i++) in sunxi_hdmi_ddc_read()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx.xml.h52 LINEAR = 0,
70 VFMT_32_FLOAT = 0,
218 RB_R5G6B5_UNORM = 0,
265 CP_ALWAYS_COUNT = 0,
298 GRAS_TSEPERF_INPUT_PRIM = 0,
316 GRAS_RASPERF_16X16_TILES = 0,
326 HLSQ_PERF_SP_VS_CONSTANT = 0,
358 PC_PCPERF_VISIBILITY_STREAMS = 0,
374 RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
394 RBBM_ALAWYS_ON = 0,
[all …]