Home
last modified time | relevance | path

Searched +full:0 +full:x07e00000 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-asus-rt-ac3100.dtsi14 memory@0 {
16 reg = <0x00000000 0x08000000>,
17 <0x88000000 0x18000000>;
22 reg = <0x1c080000 0x00180000>;
98 port@0 {
146 partition@0 {
148 reg = <0x00000000 0x00080000>;
154 reg = <0x00080000 0x00180000>;
159 reg = <0x00200000 0x07e00000>;
/openbmc/linux/lib/
H A Dbitfield_kunit.c17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
22 } while (0)
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
37 } while (0)
46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
52 } while (0)
58 } while (0)
68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants()
69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants()
70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants()
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml900 reg = <0x1b500000 0x1000>,
901 <0x1b502000 0x80>,
902 <0x1b600000 0x100>,
903 <0x0ff00000 0x100000>;
906 linux,pci-domain = <0>;
907 bus-range = <0x00 0xff>;
911 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
912 <0x82000000 0 0 0x08000000 0 0x07e00000>;
916 interrupt-map-mask = <0 0 0 0x7>;
917 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
[all …]
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/openbmc/qemu/hw/mips/
H A Dmalta.c64 #define ENVP_PADDR 0x2000
70 #define FLASH_ADDRESS 0x1e000000ULL
71 #define FPGA_ADDRESS 0x1f000000ULL
72 #define RESET_ADDRESS 0x1fc00000ULL
74 #define FLASH_SIZE 0x400000
77 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
81 MemoryRegion iomem_lo; /* 0 - 0x900 */
82 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
125 for (i = 7 ; i >= 0 ; i--) { in malta_fpga_update_display_leds()
132 leds_text[8] = '\0'; in malta_fpga_update_display_leds()
[all …]