Lines Matching +full:0 +full:x07e00000
64 #define ENVP_PADDR 0x2000
70 #define FLASH_ADDRESS 0x1e000000ULL
71 #define FPGA_ADDRESS 0x1f000000ULL
72 #define RESET_ADDRESS 0x1fc00000ULL
74 #define FLASH_SIZE 0x400000
77 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
81 MemoryRegion iomem_lo; /* 0 - 0x900 */
82 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
125 for (i = 7 ; i >= 0 ; i--) { in malta_fpga_update_display_leds()
132 leds_text[8] = '\0'; in malta_fpga_update_display_leds()
160 # define logout(fmt, ...) ((void)0)
180 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
182 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
184 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
186 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
188 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
202 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
204 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
206 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
208 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
210 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
218 uint8_t nbanks = 0; in generate_eeprom_spd()
219 uint16_t density = 0; in generate_eeprom_spd()
238 if (density & 0xff00) { in generate_eeprom_spd()
239 density = (density & 0xe0) | ((density >> 8) & 0x1f); in generate_eeprom_spd()
241 } else if (!(density & 0x1f)) { in generate_eeprom_spd()
258 spd[63] = 0; in generate_eeprom_spd()
259 for (i = 0; i < 63; i++) { in generate_eeprom_spd()
269 int i, pos = 0; in generate_eeprom_serial()
270 uint8_t mac[6] = { 0x00 }; in generate_eeprom_serial()
271 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; in generate_eeprom_serial()
274 eeprom[pos++] = 0x01; in generate_eeprom_serial()
277 eeprom[pos++] = 0x02; in generate_eeprom_serial()
280 eeprom[pos++] = 0x01; /* MAC */ in generate_eeprom_serial()
281 eeprom[pos++] = 0x06; /* length */ in generate_eeprom_serial()
286 eeprom[pos++] = 0x02; /* serial */ in generate_eeprom_serial()
287 eeprom[pos++] = 0x05; /* length */ in generate_eeprom_serial()
292 eeprom[pos] = 0; in generate_eeprom_serial()
293 for (i = 0; i < pos; i++) { in generate_eeprom_serial()
300 logout("%u: scl = %u, sda = %u, data = 0x%02x\n", in eeprom24c0x_read()
313 eeprom->command = 0; in eeprom24c0x_write()
315 } else if (eeprom->tick == 0 && !eeprom->ack) { in eeprom24c0x_write()
323 logout("\ti2c ack bit = 0\n"); in eeprom24c0x_write()
324 sda = 0; in eeprom24c0x_write()
325 eeprom->ack = 0; in eeprom24c0x_write()
327 uint8_t bit = (sda != 0); in eeprom24c0x_write()
334 logout("\tcommand 0x%04x, %s\n", eeprom->command, in eeprom24c0x_write()
340 sda = ((eeprom->data & 0x80) != 0); in eeprom24c0x_write()
348 logout("\taddress 0x%04x, data 0x%02x\n", in eeprom24c0x_write()
351 eeprom->tick = 0; in eeprom24c0x_write()
354 sda = 0; in eeprom24c0x_write()
371 uint32_t val = 0; in malta_fpga_read()
374 saddr = (addr & 0xfffff); in malta_fpga_read()
379 case 0x00200: in malta_fpga_read()
380 val = 0x00000000; in malta_fpga_read()
384 case 0x00208: in malta_fpga_read()
386 val = 0x00000012; in malta_fpga_read()
388 val = 0x00000010; in malta_fpga_read()
393 case 0x00210: in malta_fpga_read()
394 val = 0x00; in malta_fpga_read()
398 case 0x00408: in malta_fpga_read()
403 case 0x00508: in malta_fpga_read()
410 case 0x00a00: in malta_fpga_read()
417 case 0x00a08: in malta_fpga_read()
422 val = 0x00; in malta_fpga_read()
427 case 0x00b00: in malta_fpga_read()
432 case 0x00b08: in malta_fpga_read()
437 case 0x00b10: in malta_fpga_read()
442 case 0x00b18: in malta_fpga_read()
448 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", in malta_fpga_read()
461 saddr = (addr & 0xfffff); in malta_fpga_write()
466 case 0x00200: in malta_fpga_write()
470 case 0x00210: in malta_fpga_write()
474 case 0x00408: in malta_fpga_write()
475 s->leds = val & 0xff; in malta_fpga_write()
480 case 0x00410: in malta_fpga_write()
486 case 0x00418: in malta_fpga_write()
487 case 0x00420: in malta_fpga_write()
488 case 0x00428: in malta_fpga_write()
489 case 0x00430: in malta_fpga_write()
490 case 0x00438: in malta_fpga_write()
491 case 0x00440: in malta_fpga_write()
492 case 0x00448: in malta_fpga_write()
493 case 0x00450: in malta_fpga_write()
494 s->display_text[(saddr - 0x00418) >> 3] = (char) val; in malta_fpga_write()
499 case 0x00500: in malta_fpga_write()
500 if (val == 0x42) { in malta_fpga_write()
506 case 0x00508: in malta_fpga_write()
507 s->brk = val & 0xff; in malta_fpga_write()
513 case 0x00a00: in malta_fpga_write()
514 s->gpout = val & 0xff; in malta_fpga_write()
518 case 0x00b08: in malta_fpga_write()
519 s->i2coe = val & 0x03; in malta_fpga_write()
523 case 0x00b10: in malta_fpga_write()
524 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); in malta_fpga_write()
529 case 0x00b18: in malta_fpga_write()
530 s->i2csel = val & 0x01; in malta_fpga_write()
535 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", in malta_fpga_write()
551 s->leds = 0x00; in malta_fpga_reset()
552 s->brk = 0x0a; in malta_fpga_reset()
553 s->gpout = 0x00; in malta_fpga_reset()
554 s->i2cin = 0x3; in malta_fpga_reset()
555 s->i2coe = 0x0; in malta_fpga_reset()
556 s->i2cout = 0x3; in malta_fpga_reset()
557 s->i2csel = 0x1; in malta_fpga_reset()
559 s->display_text[8] = '\0'; in malta_fpga_reset()
590 "malta-fpga", 0x100000); in malta_fpga_init()
592 &s->iomem, 0, 0x900); in malta_fpga_init()
594 &s->iomem, 0xa00, 0x100000 - 0xa00); in malta_fpga_init()
597 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); in malta_fpga_init()
604 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, in malta_fpga_init()
617 pci_init_nic_in_slot(pci_bus, "pcnet", NULL, "0b"); in network_init()
637 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ in bl_setup_gt64120_jump_kernel()
639 cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), in bl_setup_gt64120_jump_kernel()
640 cpu_to_gt32(0x1be00000 << 3)); in bl_setup_gt64120_jump_kernel()
642 /* setup PCI0 io window to 0x18000000-0x181fffff */ in bl_setup_gt64120_jump_kernel()
644 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), in bl_setup_gt64120_jump_kernel()
645 cpu_to_gt32(0x18000000 << 3)); in bl_setup_gt64120_jump_kernel()
647 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), in bl_setup_gt64120_jump_kernel()
648 cpu_to_gt32(0x08000000 << 3)); in bl_setup_gt64120_jump_kernel()
652 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), in bl_setup_gt64120_jump_kernel()
653 cpu_to_gt32(0x10000000 << 3)); in bl_setup_gt64120_jump_kernel()
655 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), in bl_setup_gt64120_jump_kernel()
656 cpu_to_gt32(0x07e00000 << 3)); in bl_setup_gt64120_jump_kernel()
658 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), in bl_setup_gt64120_jump_kernel()
659 cpu_to_gt32(0x18200000 << 3)); in bl_setup_gt64120_jump_kernel()
661 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), in bl_setup_gt64120_jump_kernel()
662 cpu_to_gt32(0x0bc00000 << 3)); in bl_setup_gt64120_jump_kernel()
667 * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. in bl_setup_gt64120_jump_kernel()
672 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), in bl_setup_gt64120_jump_kernel()
674 | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 in bl_setup_gt64120_jump_kernel()
677 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), in bl_setup_gt64120_jump_kernel()
701 stw_p(p++, 0x2800); stw_p(p++, 0x001c); in write_bootloader_nanomips()
703 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
705 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
707 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
709 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
711 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
713 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
715 stw_p(p++, 0x8000); stw_p(p++, 0xc000); in write_bootloader_nanomips()
753 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ in write_bootloader()
754 ((run_addr + 0x580) & 0x0fffffff) >> 2); in write_bootloader()
755 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
758 stl_p(base + 0x500, run_addr + 0x0580); /* start: */ in write_bootloader()
759 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ in write_bootloader()
760 stl_p(base + 0x520, run_addr + 0x0580); /* start: */ in write_bootloader()
761 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ in write_bootloader()
762 stl_p(base + 0x534, run_addr + 0x0808); /* print: */ in write_bootloader()
763 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ in write_bootloader()
764 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ in write_bootloader()
765 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ in write_bootloader()
766 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ in write_bootloader()
767 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ in write_bootloader()
768 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ in write_bootloader()
769 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ in write_bootloader()
770 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ in write_bootloader()
774 p = (uint32_t *) (base + 0x580); in write_bootloader()
779 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff in write_bootloader()
780 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000 in write_bootloader()
781 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000 in write_bootloader()
788 p = (uint32_t *) (base + 0x800); in write_bootloader()
789 stl_p(p++, 0x03e00009); /* jalr ra */ in write_bootloader()
790 stl_p(p++, 0x24020000); /* li v0,0 */ in write_bootloader()
792 stl_p(p++, 0x03e06821); /* move t5,ra */ in write_bootloader()
793 stl_p(p++, 0x00805821); /* move t3,a0 */ in write_bootloader()
794 stl_p(p++, 0x00a05021); /* move t2,a1 */ in write_bootloader()
795 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ in write_bootloader()
796 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ in write_bootloader()
797 stl_p(p++, 0x10800005); /* beqz a0,834 */ in write_bootloader()
798 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
799 stl_p(p++, 0x0ff0021c); /* jal 870 */ in write_bootloader()
800 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
801 stl_p(p++, 0x1000fff9); /* b 814 */ in write_bootloader()
802 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
803 stl_p(p++, 0x01a00009); /* jalr t5 */ in write_bootloader()
804 stl_p(p++, 0x01602021); /* move a0,t3 */ in write_bootloader()
805 /* 0x83c YAMON print_count */ in write_bootloader()
806 stl_p(p++, 0x03e06821); /* move t5,ra */ in write_bootloader()
807 stl_p(p++, 0x00805821); /* move t3,a0 */ in write_bootloader()
808 stl_p(p++, 0x00a05021); /* move t2,a1 */ in write_bootloader()
809 stl_p(p++, 0x00c06021); /* move t4,a2 */ in write_bootloader()
810 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ in write_bootloader()
811 stl_p(p++, 0x0ff0021c); /* jal 870 */ in write_bootloader()
812 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
813 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ in write_bootloader()
814 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ in write_bootloader()
815 stl_p(p++, 0x1580fffa); /* bnez t4,84c */ in write_bootloader()
816 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
817 stl_p(p++, 0x01a00009); /* jalr t5 */ in write_bootloader()
818 stl_p(p++, 0x01602021); /* move a0,t3 */ in write_bootloader()
819 /* 0x870 */ in write_bootloader()
820 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ in write_bootloader()
821 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ in write_bootloader()
822 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ in write_bootloader()
823 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
824 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ in write_bootloader()
825 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ in write_bootloader()
826 stl_p(p++, 0x00000000); /* nop */ in write_bootloader()
827 stl_p(p++, 0x03e00009); /* jalr ra */ in write_bootloader()
828 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ in write_bootloader()
842 prom_buf[index] = 0; in prom_set()
859 return qemu_hexdump_line(NULL, rng_seed, sizeof(rng_seed), 0, 0); in rng_seed_hex_new()
876 int prom_index = 0; in load_kernel()
883 1, 0); in load_kernel()
884 if (kernel_size < 0) { in load_kernel()
899 initrd_size = 0; in load_kernel()
900 initrd_offset = 0; in load_kernel()
903 if (initrd_size > 0) { in load_kernel()
933 if (initrd_size > 0) { in load_kernel()
935 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", in load_kernel()
1003 return ((slot - 18) + irq_num) & 0x03; in malta_pci_slot_get_pirq()
1036 for (i = 0; i < ms->smp.cpus; i++) { in create_cpu_without_cps()
1065 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); in create_cps()
1103 int fl_idx = 0; in mips_malta_init()
1122 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); in mips_malta_init()
1126 machine->ram, 0, MIN(ram_size, 256 * MiB)); in mips_malta_init()
1127 memory_region_add_subregion(system_memory, 0, ram_low_preio); in mips_malta_init()
1146 dinfo = drive_get(IF_PFLASH, 0, fl_idx); in mips_malta_init()
1151 4, 0x0000, 0x0000, 0x0000, 0x0000, in mips_malta_init()
1188 if ((bios_size < 0 || bios_size > BIOS_SIZE) && in mips_malta_init()
1201 const size_t swapsize = MIN(bios_size, 0x3e0000); in mips_malta_init()
1231 /* Board ID = 0x420 (Malta Board with CoreLV) */ in mips_malta_init()
1232 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); in mips_malta_init()
1243 qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); in mips_malta_init()
1245 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); in mips_malta_init()
1251 qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); in mips_malta_init()
1256 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); in mips_malta_init()