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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun50i_h6.h11 #define SUNXI_SRAM_C_BASE 0x00028000
12 #define SUNXI_SRAM_A2_BASE 0x00100000
14 #define SUNXI_DE3_BASE 0x01000000
15 #define SUNXI_SS_BASE 0x01904000
16 #define SUNXI_EMCE_BASE 0x01905000
18 #define SUNXI_SRAMC_BASE 0x03000000
19 #define SUNXI_CCM_BASE 0x03001000
20 #define SUNXI_DMA_BASE 0x03002000
21 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
22 #define SUNXI_SIDC_BASE 0x03006000
[all …]
/openbmc/qemu/hw/usb/
H A Dimx-usb-phy.c31 s->usbphy[USBPHY_PWD] = 0x001e1c00; in imx_usbphy_softreset()
32 s->usbphy[USBPHY_TX] = 0x10060607; in imx_usbphy_softreset()
33 s->usbphy[USBPHY_RX] = 0x00000000; in imx_usbphy_softreset()
34 s->usbphy[USBPHY_CTRL] = 0xc0200000; in imx_usbphy_softreset()
41 s->usbphy[USBPHY_STATUS] = 0x00000000; in imx_usbphy_reset()
42 s->usbphy[USBPHY_DEBUG] = 0x7f180000; in imx_usbphy_reset()
43 s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000; in imx_usbphy_reset()
44 s->usbphy[USBPHY_DEBUG1] = 0x00001000; in imx_usbphy_reset()
45 s->usbphy[USBPHY_VERSION] = 0x04020000; in imx_usbphy_reset()
98 "%s: Read from non-existing USB PHY register 0x%" in imx_usbphy_read()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c103 u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; in gt215_link_train_calc()
105 for (i = 0; i < 8; i++) { in gt215_link_train_calc()
106 for (lo = 0; lo < 0x40; lo++) { in gt215_link_train_calc()
107 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
109 if (vals[lo] & (0x101 << i)) in gt215_link_train_calc()
113 if (lo == 0x40) in gt215_link_train_calc()
116 for (hi = lo + 1; hi < 0x40; hi++) { in gt215_link_train_calc()
117 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
119 if (!(vals[hi] & (0x101 << i))) { in gt215_link_train_calc()
126 bins[(median[i] & 0xf0) >> 4]++; in gt215_link_train_calc()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8916-mss-pil.yaml253 reg = <0x04080000 0x100>, <0x04020000 0x40>;
257 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
263 qcom,smem-states = <&hexagon_smp2p_out 0>;
265 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
277 resets = <&scm 0>;
285 qcom,smd-edge = <0>;
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h26 #define KS2_DDRPHY_PIR_OFFSET 0x04
27 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
28 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
29 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
30 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
31 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
32 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
33 #define KS2_DDRPHY_PTR1_OFFSET 0x20
34 #define KS2_DDRPHY_PTR2_OFFSET 0x24
35 #define KS2_DDRPHY_PTR3_OFFSET 0x28
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun50i-h6.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
51 #clock-cells = <0>;
59 #clock-cells = <0>;
66 #clock-cells = <0>;
97 reg = <0x03001000 0x1000>;
106 reg = <0x03021000 0x1000>,
107 <0x03022000 0x2000>,
108 <0x03024000 0x2000>,
[all …]
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-lpddr3-samsung-4GB-1866.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
18 0x801d181e
19 0x17050a08
[all …]
/openbmc/qemu/hw/scsi/
H A Dmfi.h44 #define MFI_IMSG0 0x10 /* Inbound message 0 */
45 #define MFI_IMSG1 0x14 /* Inbound message 1 */
46 #define MFI_OMSG0 0x18 /* Outbound message 0 */
47 #define MFI_OMSG1 0x1c /* Outbound message 1 */
48 #define MFI_IDB 0x20 /* Inbound doorbell */
49 #define MFI_ISTS 0x24 /* Inbound interrupt status */
50 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
51 #define MFI_ODB 0x2c /* Outbound doorbell */
52 #define MFI_OSTS 0x30 /* Outbound interrupt status */
53 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
66 reg = <0x0 0x40000000 0x0 0x40000>;
72 #clock-cells = <0>;
109 ranges = <0x0 0x0 0x0 0x40000000>;
113 reg = <0x03000000 0x1000>;
120 reg = <0x00028000 0x30000>;
123 ranges = <0 0x00028000 0x30000>;
129 reg = <0x03001000 0x1000>;
[all …]
H A Dsun50i-h6.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
27 reg = <0>;
72 #clock-cells = <0>;
114 reg = <0x1000000 0x400000>;
118 ranges = <0 0x1000000 0x400000>;
120 display_clocks: clock@0 {
122 reg = <0x0 0x10000>;
133 compatible = "allwinner,sun50i-h6-de3-mixer-0";
134 reg = <0x100000 0x100000>;
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_device.c25 .chip_ids = ADRENO_CHIP_IDS(0x02000000),
36 .chip_ids = ADRENO_CHIP_IDS(0x02000001),
47 .chip_ids = ADRENO_CHIP_IDS(0x02020000),
59 0x03000512,
60 0x03000520
72 .chip_ids = ADRENO_CHIP_IDS(0x03000600),
84 0x03020000,
85 0x03020001,
86 0x03020002
99 0x03030000,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Ddm.c25 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
26 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
29 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
30 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
33 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
34 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
37 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
47 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
48 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
57 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; in rtl92ee_dm_false_alarm_counter_statistics()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
[all …]
H A Dmsm8939.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
48 reg = <0x100>;
66 reg = <0x101>;
79 reg = <0x102>;
92 reg = <0x103>;
101 CPU4: cpu@0 {
105 reg = <0x0>;
123 reg = <0x1>;
[all …]
H A Dmsm8916.dtsi26 reg = <0 0x80000000 0 0>;
35 reg = <0x0 0x86000000 0x0 0x300000>;
41 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 reg = <0x0 0x89300000 0x0 0x600000>;
[all …]
/openbmc/qemu/disas/
H A Dmips.c82 #define OP_MASK_OP 0x3f
84 #define OP_MASK_RS 0x1f
86 #define OP_MASK_FR 0x1f
88 #define OP_MASK_FMT 0x1f
90 #define OP_MASK_BCC 0x7
92 #define OP_MASK_CODE 0x3ff
94 #define OP_MASK_CODE2 0x3ff
96 #define OP_MASK_RT 0x1f
98 #define OP_MASK_FT 0x1f
100 #define OP_MASK_CACHE 0x1f
[all …]