Lines Matching +full:0 +full:x04020000
44 #define MFI_IMSG0 0x10 /* Inbound message 0 */
45 #define MFI_IMSG1 0x14 /* Inbound message 1 */
46 #define MFI_OMSG0 0x18 /* Outbound message 0 */
47 #define MFI_OMSG1 0x1c /* Outbound message 1 */
48 #define MFI_IDB 0x20 /* Inbound doorbell */
49 #define MFI_ISTS 0x24 /* Inbound interrupt status */
50 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
51 #define MFI_ODB 0x2c /* Outbound doorbell */
52 #define MFI_OSTS 0x30 /* Outbound interrupt status */
53 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
54 #define MFI_IQP 0x40 /* Inbound queue port */
55 #define MFI_OQP 0x44 /* Outbound queue port */
60 #define MFI_ODR0 0x9c /* outbound doorbell register0 */
61 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */
62 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */
63 #define MFI_OSP1 0xb4 /* outbound scratch pad1 */
64 #define MFI_IQPL 0xc0 /* Inbound queue port (low bytes) */
65 #define MFI_IQPH 0xc4 /* Inbound queue port (high bytes) */
66 #define MFI_DIAG 0xf8 /* Host diag */
67 #define MFI_SEQ 0xfc /* Sequencer offset */
68 #define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */
69 #define MFI_RMI 0x2 /* reply message interrupt */
70 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
71 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */
76 #define MFI_GEN2_EIM 0x00000005 /* gen2 enable interrupt mask */
77 #define MFI_GEN2_RM 0x00000001 /* reply gen2 message interrupt */
82 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */
83 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */
86 #define MFI_OSTS_INTR_VALID 0x00000002
91 #define MFI_FWSTATE_MASK 0xf0000000
92 #define MFI_FWSTATE_UNDEFINED 0x00000000
93 #define MFI_FWSTATE_BB_INIT 0x10000000
94 #define MFI_FWSTATE_FW_INIT 0x40000000
95 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000
96 #define MFI_FWSTATE_FW_INIT_2 0x70000000
97 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000
98 #define MFI_FWSTATE_BOOT_MSG_PENDING 0x90000000
99 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000
100 #define MFI_FWSTATE_READY 0xb0000000
101 #define MFI_FWSTATE_OPERATIONAL 0xc0000000
102 #define MFI_FWSTATE_FAULT 0xf0000000
103 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000
104 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff
105 #define MFI_FWSTATE_MSIX_SUPPORTED 0x04000000
106 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000
112 #define MFI_FWINIT_ABORT 0x00000001 /* Abort all pending commands */
113 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */
114 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */
115 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
116 #define MFI_FWINIT_HOTPLUG 0x00000010
117 #define MFI_FWINIT_STOP_ADP 0x00000020 /* Move to operational, stop */
118 #define MFI_FWINIT_ADP_RESET 0x00000040 /* Reset ADP */
123 #define MFI_DIAG_WRITE_ENABLE 0x00000080
124 #define MFI_DIAG_RESET_ADP 0x00000004
128 MFI_CMD_INIT = 0x00,
141 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC = 0x0100e100,
142 MFI_DCMD_CTRL_GET_INFO = 0x01010000,
143 MFI_DCMD_CTRL_GET_PROPERTIES = 0x01020100,
144 MFI_DCMD_CTRL_SET_PROPERTIES = 0x01020200,
145 MFI_DCMD_CTRL_ALARM = 0x01030000,
146 MFI_DCMD_CTRL_ALARM_GET = 0x01030100,
147 MFI_DCMD_CTRL_ALARM_ENABLE = 0x01030200,
148 MFI_DCMD_CTRL_ALARM_DISABLE = 0x01030300,
149 MFI_DCMD_CTRL_ALARM_SILENCE = 0x01030400,
150 MFI_DCMD_CTRL_ALARM_TEST = 0x01030500,
151 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
152 MFI_DCMD_CTRL_EVENT_CLEAR = 0x01040200,
153 MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
154 MFI_DCMD_CTRL_EVENT_COUNT = 0x01040400,
155 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
156 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
157 MFI_DCMD_HIBERNATE_STANDBY = 0x01060000,
158 MFI_DCMD_CTRL_GET_TIME = 0x01080101,
159 MFI_DCMD_CTRL_SET_TIME = 0x01080102,
160 MFI_DCMD_CTRL_BIOS_DATA_GET = 0x010c0100,
161 MFI_DCMD_CTRL_BIOS_DATA_SET = 0x010c0200,
162 MFI_DCMD_CTRL_FACTORY_DEFAULTS = 0x010d0000,
163 MFI_DCMD_CTRL_MFC_DEFAULTS_GET = 0x010e0201,
164 MFI_DCMD_CTRL_MFC_DEFAULTS_SET = 0x010e0202,
165 MFI_DCMD_CTRL_CACHE_FLUSH = 0x01101000,
166 MFI_DCMD_PD_GET_LIST = 0x02010000,
167 MFI_DCMD_PD_LIST_QUERY = 0x02010100,
168 MFI_DCMD_PD_GET_INFO = 0x02020000,
169 MFI_DCMD_PD_STATE_SET = 0x02030100,
170 MFI_DCMD_PD_REBUILD = 0x02040100,
171 MFI_DCMD_PD_BLINK = 0x02070100,
172 MFI_DCMD_PD_UNBLINK = 0x02070200,
173 MFI_DCMD_LD_GET_LIST = 0x03010000,
174 MFI_DCMD_LD_LIST_QUERY = 0x03010100,
175 MFI_DCMD_LD_GET_INFO = 0x03020000,
176 MFI_DCMD_LD_GET_PROP = 0x03030000,
177 MFI_DCMD_LD_SET_PROP = 0x03040000,
178 MFI_DCMD_LD_DELETE = 0x03090000,
179 MFI_DCMD_CFG_READ = 0x04010000,
180 MFI_DCMD_CFG_ADD = 0x04020000,
181 MFI_DCMD_CFG_CLEAR = 0x04030000,
182 MFI_DCMD_CFG_FOREIGN_READ = 0x04060100,
183 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
184 MFI_DCMD_BBU_STATUS = 0x05010000,
185 MFI_DCMD_BBU_CAPACITY_INFO = 0x05020000,
186 MFI_DCMD_BBU_DESIGN_INFO = 0x05030000,
187 MFI_DCMD_BBU_PROP_GET = 0x05050100,
188 MFI_DCMD_CLUSTER = 0x08000000,
189 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
190 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
194 #define MFI_FLUSHCACHE_CTRL 0x01
195 #define MFI_FLUSHCACHE_DISK 0x02
198 #define MFI_SHUTDOWN_SPINDOWN 0x01
204 MFI_FRAME_DONT_POST_IN_REPLY_QUEUE = 0x0001,
205 MFI_FRAME_SGL64 = 0x0002,
206 MFI_FRAME_SENSE64 = 0x0004,
207 MFI_FRAME_DIR_WRITE = 0x0008,
208 MFI_FRAME_DIR_READ = 0x0010,
209 MFI_FRAME_IEEE_SGL = 0x0020,
214 MFI_STAT_OK = 0x00,
230 MFI_STAT_FLASH_ERROR = 0x10,
246 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
262 MFI_STAT_SHUTDOWN_FAILED = 0x30,
278 MFI_STAT_MULTIPLE_PDS_IN_ARRAY = 0x40,
294 MFI_STAT_CONFIG_FDE_NON_FDE_MIX_NOT_ALLOWED = 0x50,
310 MFI_STAT_IO_METRICS_DISABLED = 0x60,
316 MFI_STAT_INVALID_STATUS = 0xFF
323 MFI_EVT_CLASS_INFO = 0,
332 MFI_EVT_LOCALE_LD = 0x0001,
333 MFI_EVT_LOCALE_PD = 0x0002,
334 MFI_EVT_LOCALE_ENCL = 0x0004,
335 MFI_EVT_LOCALE_BBU = 0x0008,
336 MFI_EVT_LOCALE_SAS = 0x0010,
337 MFI_EVT_LOCALE_CTRL = 0x0020,
338 MFI_EVT_LOCALE_CONFIG = 0x0040,
339 MFI_EVT_LOCALE_CLUSTER = 0x0080,
340 MFI_EVT_LOCALE_ALL = 0xffff
345 MR_EVT_ARGS_NONE = 0x00,
385 #define MR_EVT_CFG_CLEARED 0x0004
386 #define MR_EVT_CTRL_SHUTDOWN 0x002a
387 #define MR_EVT_LD_STATE_CHANGE 0x0051
388 #define MR_EVT_PD_INSERTED 0x005b
389 #define MR_EVT_PD_REMOVED 0x0070
390 #define MR_EVT_PD_STATE_CHANGED 0x0072
391 #define MR_EVT_LD_CREATED 0x008a
392 #define MR_EVT_LD_DELETED 0x008b
393 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
394 #define MR_EVT_LD_OFFLINE 0x00fc
395 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
398 MR_LD_CACHE_WRITE_BACK = 0x01,
399 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
400 MR_LD_CACHE_READ_AHEAD = 0x04,
401 MR_LD_CACHE_READ_ADAPTIVE = 0x08,
402 MR_LD_CACHE_WRITE_CACHE_BAD_BBU = 0x10,
403 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
404 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
408 MR_PD_CACHE_UNCHANGED = 0,
414 MR_PD_QUERY_TYPE_ALL = 0,
423 MR_LD_QUERY_TYPE_ALL = 0,
570 #define MFI_QUEUE_FLAG_CONTEXT64 0x00000002
614 /* set TRUE to disable copyBack (0=copyback enabled) */
615 #define MFI_CTRL_PROP_CopyBackDisabled (1 << 0)
638 * capacity. 0=READ only
642 * is spun down (0=use FW defaults)
659 #define MFI_INFO_HOST_PCIX 0x01
660 #define MFI_INFO_HOST_PCIE 0x02
661 #define MFI_INFO_HOST_ISCSI 0x04
662 #define MFI_INFO_HOST_SAS3G 0x08
671 #define MFI_INFO_DEV_SPI 0x01
672 #define MFI_INFO_DEV_SAS3G 0x02
673 #define MFI_INFO_DEV_SATA1 0x04
674 #define MFI_INFO_DEV_SATA3G 0x08
675 #define MFI_INFO_DEV_PCIE 0x10
766 #define MFI_INFO_HW_BBU 0x01
767 #define MFI_INFO_HW_ALARM 0x02
768 #define MFI_INFO_HW_NVRAM 0x04
769 #define MFI_INFO_HW_UART 0x08
770 #define MFI_INFO_HW_MEM 0x10
771 #define MFI_INFO_HW_FLASH 0x20
793 #define MFI_INFO_RAID_0 0x01
794 #define MFI_INFO_RAID_1 0x02
795 #define MFI_INFO_RAID_5 0x04
796 #define MFI_INFO_RAID_1E 0x08
797 #define MFI_INFO_RAID_6 0x10
800 #define MFI_INFO_AOPS_RBLD_RATE 0x0001
801 #define MFI_INFO_AOPS_CC_RATE 0x0002
802 #define MFI_INFO_AOPS_BGI_RATE 0x0004
803 #define MFI_INFO_AOPS_RECON_RATE 0x0008
804 #define MFI_INFO_AOPS_PATROL_RATE 0x0010
805 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
806 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
807 #define MFI_INFO_AOPS_BBU 0x0080
808 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
809 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
810 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
811 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
812 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
813 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
814 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
817 #define MFI_INFO_LDOPS_READ_POLICY 0x01
818 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02
819 #define MFI_INFO_LDOPS_IO_POLICY 0x04
820 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
821 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
830 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
831 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
832 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
835 #define MFI_INFO_PDMIX_SAS 0x01
836 #define MFI_INFO_PDMIX_SATA 0x02
837 #define MFI_INFO_PDMIX_ENCL 0x04
838 #define MFI_INFO_PDMIX_LD 0x08
839 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
844 char package_version[0x60];
845 uint8_t pad[0x800 - 0x6a0];
1021 #define MFI_PD_DDF_TYPE_FORCED_PD_GUID (1 << 0)
1040 #define PD_PROGRESS_ACTIVE_REBUILD (1 << 0)
1129 MFI_LD_ACCESS_RW = 0,
1136 MFI_LD_STATE_OFFLINE = 0,
1143 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1144 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
1145 MFI_PD_STATE_HOT_SPARE = 0x02,
1146 MFI_PD_STATE_OFFLINE = 0x10,
1147 MFI_PD_STATE_FAILED = 0x11,
1148 MFI_PD_STATE_REBUILD = 0x14,
1149 MFI_PD_STATE_ONLINE = 0x18,
1150 MFI_PD_STATE_COPYBACK = 0x20,
1151 MFI_PD_STATE_SYSTEM = 0x40
1180 #define MFI_LD_PROGRESS_CC (1<<0)
1218 #define MFI_SPARE_IS_DEDICATED (1 << 0)