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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65.dtsi59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
60 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
61 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
62 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
63 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
65 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
66 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
67 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
68 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
69 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
H A Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
26 reg = <0x0 0x40f04200 0x0 0x10>;
29 pinctrl-single,function-mask = <0x00000101>;
35 reg = <0x0 0x40f04280 0x0 0x8>;
38 pinctrl-single,function-mask = <0x00000003>;
43 reg = <0x00 0x40a00000 0x00 0x100>;
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x43000014 0x00 0x4>;
46 reg = <0x00 0x43600000 0x00 0x10000>,
47 <0x00 0x44880000 0x00 0x20000>,
48 <0x00 0x44860000 0x00 0x20000>;
59 reg = <0x00 0x41c00000 0x00 0x100000>;
60 ranges = <0x00 0x00 0x41c00000 0x100000>;
67 /* Proxy 0 addressing */
68 reg = <0x00 0x4301c000 0x00 0x034>;
71 pinctrl-single,function-mask = <0xffffffff>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi20 reg = <0x00 0x44083000 0x00 0x1000>;
44 reg = <0x00 0x43000014 0x00 0x4>;
51 reg = <0x00 0x43600000 0x00 0x10000>,
52 <0x00 0x44880000 0x00 0x20000>,
53 <0x00 0x44860000 0x00 0x20000>;
64 reg = <0x00 0x41c00000 0x00 0x100000>;
65 ranges = <0x00 0x00 0x41c00000 0x100000>;
72 /* Proxy 0 addressing */
73 reg = <0x00 0x4301c000 0x00 0x034>;
76 pinctrl-single,function-mask = <0xffffffff>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
68 reg = <0x00 0x40f04200 0x00 0x28>;
71 pinctrl-single,function-mask = <0x0000000f>;
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau8810.h11 #define NR_ADB 0x10
12 #define NR_WT 0x00
13 #define NR_SRC 0x10
14 #define NR_A3D 0x10
15 #define NR_MIXIN 0x20
16 #define NR_MIXOUT 0x10
20 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
21 #define POS_MASK 0x00000fff
22 #define POS_SHIFT 0x0
23 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-r5f-rproc.yaml72 It should be either a value of 1 (LockStep mode) or 0 (Split mode) on
76 It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and
103 either of them can be configured to appear at that R5F's address 0x0.
177 enum: [0, 1]
181 either a value of 1 (enabled) or 0 (disabled), default is disabled
186 enum: [0, 1]
190 either a value of 1 (enabled) or 0 (disabled), default is enabled if
195 enum: [0, 1]
198 address 0 (from core's view). Should be either a value of 1 (ATCM
199 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]