/openbmc/linux/Documentation/devicetree/bindings/mtd/ |
H A D | ti,gpmc-onenand.yaml | 19 pattern: "^onenand@[0-9],[0,9]$" 38 "@[0-9a-f]+$": 56 reg = <0x6e000000 0x02d0>; 65 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ 66 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ 68 onenand@0,0 { 70 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ 74 partition@0 { 76 reg = <0x00000000 0x00100000>; 81 reg = <0x00100000 0x002c0000>;
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx6ul-pinfunc.h | 17 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 18 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 20 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 21 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 22 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 23 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 24 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 25 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 26 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 27 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 [all …]
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H A D | imx7d-pinfunc.h | 18 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 19 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 20 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 23 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 24 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 25 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 [all …]
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H A D | k3-am654-base-board-u-boot.dtsi | 23 reg = <0x0 0x11c000 0x0 0x2e4>; 26 pinctrl-single,function-mask = <0xffffffff>; 31 reg = <0x0 0x11c2e8 0x0 0x24>; 34 pinctrl-single,function-mask = <0xffffffff>; 39 reg = <0x0 0x4F80000 0x0 0x1000>, 40 <0x0 0x4F90000 0x0 0x400>; 48 reg = <0x0 0x4FA0000 0x0 0x1000>, 49 <0x0 0x4FB0000 0x0 0x400>; 61 reg = <0x0 0x4301c000 0x0 0x118>; 64 pinctrl-single,function-mask = <0xffffffff>; [all …]
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H A D | imx7ulp-pinfunc.h | 26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7d-pinfunc.h | 14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 [all …]
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H A D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 [all …]
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H A D | imx7ulp-pinfunc.h | 15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 [all …]
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/openbmc/linux/include/linux/mmc/ |
H A D | sdio_ids.h | 13 #define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */ 14 #define SDIO_CLASS_UART 0x01 /* standard UART interface */ 15 #define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */ 16 #define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */ 17 #define SDIO_CLASS_GPS 0x04 /* GPS standard interface */ 18 #define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */ 19 #define SDIO_CLASS_PHS 0x06 /* PHS standard interface */ 20 #define SDIO_CLASS_WLAN 0x07 /* WLAN interface */ 21 #define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */ 22 #define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */ [all …]
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/openbmc/linux/drivers/net/can/spi/mcp251xfd/ |
H A D | mcp251xfd-crc16.c | 24 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011, 25 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022, 26 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072, 27 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041, 28 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2, 29 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1, 30 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1, 31 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082, 32 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192, 33 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1, [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx93-pinfunc.h | 13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 [all …]
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/openbmc/linux/arch/ia64/include/uapi/asm/ |
H A D | ptrace_offsets.h | 77 #define PT_F32 0x0000 78 #define PT_F33 0x0010 79 #define PT_F34 0x0020 80 #define PT_F35 0x0030 81 #define PT_F36 0x0040 82 #define PT_F37 0x0050 83 #define PT_F38 0x0060 84 #define PT_F39 0x0070 85 #define PT_F40 0x0080 86 #define PT_F41 0x0090 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_1_0_d.h | 26 #define ixCLIENT0_BM 0x0220 27 #define ixCLIENT0_CD0 0x0210 28 #define ixCLIENT0_CD1 0x0214 29 #define ixCLIENT0_CD2 0x0218 30 #define ixCLIENT0_CD3 0x021C 31 #define ixCLIENT0_CK0 0x0200 32 #define ixCLIENT0_CK1 0x0204 33 #define ixCLIENT0_CK2 0x0208 34 #define ixCLIENT0_CK3 0x020C 35 #define ixCLIENT0_K0 0x01F0 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx7/ |
H A D | mx7d_pins.h | 12 …0__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, … 13 MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), 14 …0__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, … 16 …1__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, … 17 …1__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, … 18 …1__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, … 19 …MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0… 21 …2__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, … 22 …2__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, … 23 …2__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, … [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
H A D | iomux-vf610.h | 46 VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), 47 VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), 48 VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 49 VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 50 VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 51 VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 52 VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 53 VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 54 VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), 55 VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), [all …]
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/openbmc/linux/drivers/media/i2c/ |
H A D | saa7115.c | 49 MODULE_PARM_DESC(debug, "Debug level (0-1)"); 120 return reg < 0x20 && reg != 0x01 && reg != 0x0f && in saa711x_has_reg() 121 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; in saa711x_has_reg() 123 return reg < 0x20 && reg != 0x01 && reg != 0x0f && in saa711x_has_reg() 124 reg != 0x14 && reg != 0x18 && reg != 0x19 && in saa711x_has_reg() 125 reg != 0x1d && reg != 0x1e; in saa711x_has_reg() 128 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || in saa711x_has_reg() 129 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || in saa711x_has_reg() 130 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || in saa711x_has_reg() 131 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) in saa711x_has_reg() [all …]
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/openbmc/linux/arch/s390/include/asm/ |
H A D | lowcore.h | 25 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */ 26 __u32 ipl_parmblock_ptr; /* 0x0014 */ 27 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */ 28 __u32 ext_params; /* 0x0080 */ 31 __u16 ext_cpu_addr; /* 0x0084 */ 32 __u16 ext_int_code; /* 0x0086 */ 36 __u32 svc_int_code; /* 0x0088 */ 39 __u16 pgm_ilc; /* 0x008c */ 40 __u16 pgm_code; /* 0x008e */ 44 __u32 data_exc_code; /* 0x0090 */ [all …]
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/openbmc/qemu/hw/display/ |
H A D | ati_dbg.c | 11 {"MM_INDEX", 0x0000}, 12 {"MM_DATA", 0x0004}, 13 {"CLOCK_CNTL_INDEX", 0x0008}, 14 {"CLOCK_CNTL_DATA", 0x000c}, 15 {"BIOS_0_SCRATCH", 0x0010}, 16 {"BUS_CNTL", 0x0030}, 17 {"BUS_CNTL1", 0x0034}, 18 {"GEN_INT_CNTL", 0x0040}, 19 {"GEN_INT_STATUS", 0x0044}, 20 {"CRTC_GEN_CNTL", 0x0050}, [all …]
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H A D | ati_regs.h | 17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space 18 * 0x0100-0x0eff Misc regs only accessible via mmio 19 * 0x0f00-0x0fff Read-only copy of PCI config regs 20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs 21 * 0x1400-0x1fff GUI (drawing engine) regs 29 #define MM_INDEX 0x0000 30 #define MM_DATA 0x0004 31 #define CLOCK_CNTL_INDEX 0x0008 32 #define CLOCK_CNTL_DATA 0x000c 33 #define BIOS_0_SCRATCH 0x0010 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
H A D | mx6ull_pins.h | 12 …DE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, … 13 …DE1__GPIO5_IO11 = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, … 17 * TAMPER_PIN_DISABLE[1:0] settings. 19 …PER0__GPIO5_IO00 = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, … 20 …PER1__GPIO5_IO01 = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, … 21 …PER2__GPIO5_IO02 = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, … 22 …PER3__GPIO5_IO03 = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, … 23 …PER4__GPIO5_IO04 = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, … 24 …PER5__GPIO5_IO05 = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, … 25 …PER6__GPIO5_IO06 = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, … [all …]
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H A D | mx6ul_pins.h | 13 …MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0… 14 …MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0… 17 * fusemap TAMPER_PIN_DISABLE[1:0] settings. 19 …MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0… 20 …MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0… 21 …MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0… 22 …MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0… 23 …MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0… 24 …MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0… 25 …MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0… [all …]
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/openbmc/linux/include/video/ |
H A D | aty128.h | 13 #define CLOCK_CNTL_INDEX 0x0008 14 #define CLOCK_CNTL_DATA 0x000c 15 #define BIOS_0_SCRATCH 0x0010 16 #define BUS_CNTL 0x0030 17 #define BUS_CNTL1 0x0034 18 #define GEN_INT_CNTL 0x0040 19 #define CRTC_GEN_CNTL 0x0050 20 #define CRTC_EXT_CNTL 0x0054 21 #define DAC_CNTL 0x0058 22 #define I2C_CNTL_1 0x0094 [all …]
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H A D | sstfb.h | 27 # define SST_DEBUG_REG 0 28 # define SST_DEBUG_FUNC 0 29 # define SST_DEBUG_VAR 0 32 #if (SST_DEBUG_REG > 0) 43 #if (SST_DEBUG_FUNC > 0) 59 #if (SST_DEBUG_VAR > 0) 81 #define PCI_INIT_ENABLE 0x40 82 # define PCI_EN_INIT_WR BIT(0) 85 #define PCI_VCLK_ENABLE 0xc0 /* enable video */ 86 #define PCI_VCLK_DISABLE 0xe0 [all …]
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/openbmc/qemu/target/xtensa/core-lx106/ |
H A D | gdb-config.c.inc | 23 XTREG( 0, 0,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) 24 XTREG( 1, 4,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) 25 XTREG( 2, 8,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) 26 XTREG( 3, 12,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) 27 XTREG( 4, 16,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) 28 XTREG( 5, 20,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) 29 XTREG( 6, 24,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) 30 XTREG( 7, 28,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) 31 XTREG( 8, 32,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) 32 XTREG( 9, 36,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) [all …]
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/openbmc/linux/drivers/net/phy/mscc/ |
H A D | mscc_ptp.h | 13 #define BIU_ADDR_EXE 0x8000 14 #define BIU_ADDR_READ 0x4000 15 #define BIU_ADDR_WRITE 0x0000 23 #define MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS 0x002d 24 #define MSCC_PHY_1588_VSC85XX_INT_STATUS 0x004d 25 #define VSC85XX_1588_INT_FIFO_ADD 0x0004 26 #define VSC85XX_1588_INT_FIFO_OVERFLOW 0x0001 28 #define MSCC_PHY_1588_INGR_VSC85XX_INT_MASK 0x002e 29 #define MSCC_PHY_1588_VSC85XX_INT_MASK 0x004e 34 #define MSCC_PHY_ANA_ETH1_NTX_PROT 0x0000 [all …]
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