Home
last modified time | relevance | path

Searched +full:0 +full:x02020000 (Results 1 – 25 of 41) sorted by relevance

12

/openbmc/linux/arch/arm/include/debug/
H A Dimx-uart.h9 #define IMX1_UART1_BASE_ADDR 0x00206000
10 #define IMX1_UART2_BASE_ADDR 0x00207000
14 #define IMX25_UART1_BASE_ADDR 0x43f90000
15 #define IMX25_UART2_BASE_ADDR 0x43f94000
16 #define IMX25_UART3_BASE_ADDR 0x5000c000
17 #define IMX25_UART4_BASE_ADDR 0x50008000
18 #define IMX25_UART5_BASE_ADDR 0x5002c000
22 #define IMX27_UART1_BASE_ADDR 0x1000a000
23 #define IMX27_UART2_BASE_ADDR 0x1000b000
24 #define IMX27_UART3_BASE_ADDR 0x1000c000
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
79 reg = <0x101c0000 0xb00>;
96 reg = <0x101d0000 0x100>;
102 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]
H A Dexynos4x12.dtsi70 #interconnect-cells = <0>;
80 #interconnect-cells = <0>;
120 #interconnect-cells = <0>;
211 reg = <0x11400000 0x1000>;
217 reg = <0x11000000 0x1000>;
229 reg = <0x03860000 0x1000>;
231 interrupts = <10 0>;
236 reg = <0x106e0000 0x1000>;
242 reg = <0x02020000 0x40000>;
245 ranges = <0 0x02020000 0x40000>;
[all …]
H A Dexynos3250.dtsi199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
/openbmc/u-boot/include/configs/
H A Dexynos5420-common.h21 #define CONFIG_SPL_TEXT_BASE 0x02024410
23 #define CONFIG_SPL_TEXT_BASE 0x02024400
25 #define CONFIG_IRAM_TOP 0x02074000
32 #define CONFIG_PHY_IRAM_BASE 0x02020000
35 #define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000)
40 #define CONFIG_LOWPOWER_FLAG 0x02020028
41 #define CONFIG_LOWPOWER_ADDR 0x0202002C
H A Darndale.h12 "fdtfile=exynos5250-arndale.dtb\0"
27 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
31 #define CONFIG_IRAM_STACK 0x02050000
41 #define CONFIG_S5P_PA_SYSRAM 0x02020000
45 #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
163 ranges = <0 0x5c000000 0x40000>;
166 reg = <0x100 0x50>;
170 reg = <0x1000 0x1000>;
175 reg = <0x20000 0x20000>;
190 reg = <0x02020000 0x54000>;
193 ranges = <0 0x02020000 0x54000>;
195 smp-sram@0 {
197 reg = <0x0 0x1000>;
202 reg = <0x53000 0x1000>;
[all …]
/openbmc/qemu/tests/qtest/
H A Dmegasas-test.c58 bar = qpci_iomap(dev, 0, NULL); in megasas_pd_get_info_fuzz()
60 memset(context, 0, sizeof(context)); in megasas_pd_get_info_fuzz()
61 context[0] = cpu_to_le32(0x05050505); in megasas_pd_get_info_fuzz()
62 context[1] = cpu_to_le32(0x01010101); in megasas_pd_get_info_fuzz()
64 context[i] = cpu_to_le32(0x41414141); in megasas_pd_get_info_fuzz()
66 context[6] = cpu_to_le32(0x02020000); in megasas_pd_get_info_fuzz()
67 context[7] = cpu_to_le32(0); in megasas_pd_get_info_fuzz()
71 qpci_io_writel(dev, bar, 0x40, context_pa); in megasas_pd_get_info_fuzz()
80 .after_cmd_line = "-device scsi-hd,bus=scsi0.0,drive=drv0", in megasas_register_nodes()
83 add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) }); in megasas_register_nodes()
/openbmc/qemu/include/hw/arm/
H A Dexynos4210.h38 #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
39 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
40 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
42 #define EXYNOS4210_IROM_BASE_ADDR 0x00000000
43 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
44 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
45 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
47 #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
48 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
52 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000
[all …]
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
24 cpu@0 {
27 reg = <0x0 0x0>;
34 reg = <0x0 0x1>;
41 reg = <0x0 0x2>;
48 reg = <0x0 0x3>;
66 reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
67 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dsec_boot.S14 ldr r2, =0x02073000 @ r2: target address
28 * This workaround code is relocated to the address 0x02073000
30 * (Base Address - 0x02020000, Limit Address - 0x020740000).
43 * Resume address - 0x2073008
44 * Resume flag - 0x207300C
47 * Switch address - 0x2073018
50 * Hotplug address - 0x207301C
53 * C2 address - 0x2073024
56 * CPU0 state - 0x2073028
57 * CPU1 state - 0x207302C
[all …]
/openbmc/qemu/hw/misc/
H A Darm_l2x0.c30 #define CACHE_ID 0x410000c8
69 offset &= 0xfff; in l2x0_priv_read()
70 if (offset >= 0x730 && offset < 0x800) { in l2x0_priv_read()
71 return 0; /* cache ops complete */ in l2x0_priv_read()
74 case 0: in l2x0_priv_read()
76 case 0x4: in l2x0_priv_read()
81 case 0x100: in l2x0_priv_read()
83 case 0x104: in l2x0_priv_read()
85 case 0x108: in l2x0_priv_read()
87 case 0x10C: in l2x0_priv_read()
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_mem_init.c23 0x00000000, 0x00000000, 0x00000000, 0x00000000,
24 0x00000000, 0x00000000, 0x00000000, 0x00000000,
25 0x00000000, 0x00000000, 0x00000000, 0x00000000,
26 0x00000000, 0x00000000, 0x00000000, 0x00000000,
27 0x00000000, 0x00000100, 0x00000000, 0x00000000,
28 0x00000000, 0x00000000, 0x00000000, 0x00000000,
29 0x00000000, 0x00000000, 0x00010101, 0x01010101,
30 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
31 0x00000100, 0x00000100, 0x00000000, 0x00000002,
32 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
[all …]
/openbmc/linux/net/smc/
H A Dsmc_clc.h22 #define SMC_CLC_PROPOSAL 0x01
23 #define SMC_CLC_ACCEPT 0x02
24 #define SMC_CLC_CONFIRM 0x03
25 #define SMC_CLC_DECLINE 0x04
27 #define SMC_TYPE_R 0 /* SMC-R only */
33 #define SMC_CLC_DECL_MEM 0x01010000 /* insufficient memory resources */
34 #define SMC_CLC_DECL_TIMEOUT_CL 0x02010000 /* timeout w4 QP confirm link */
35 #define SMC_CLC_DECL_TIMEOUT_AL 0x02020000 /* timeout w4 QP add link */
36 #define SMC_CLC_DECL_CNFERR 0x03000000 /* configuration error */
37 #define SMC_CLC_DECL_PEERNOSMC 0x03010000 /* peer did not indicate SMC */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5250-snow.dts46 reg = <0x40000000 0x80000000>;
55 reg = <0x02020000 0x60000>;
59 samsung,bl1-offset = <0x1400>;
60 samsung,bl2-offset = <0x3400>;
62 u-boot-offset = <0x3e00000 0x100000>;
66 reg = <0 0x100000>;
71 reg = <0 0x2000>;
80 reg = <0x2000 0x4000>;
90 reg = <0x6000 0xb0000>;
100 #size-cells = <0>;
[all …]
H A Dexynos5250-spring.dts40 reg = <0x40000000 0x80000000>;
44 reg = <0x02020000 0x60000>;
48 samsung,bl1-offset = <0x1400>;
49 samsung,bl2-offset = <0x3400>;
51 u-boot-offset = <0x3e00000 0x100000>;
54 flash@0 {
55 reg = <0 0x100000>;
60 reg = <0 0x2000>;
69 reg = <0x2000 0x8000>;
79 reg = <0xa000 0xb0000>;
[all …]
H A Dimx6sll.dtsi44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
85 reg = <0x00a01000 0x1000>,
86 <0x00a00100 0x100>;
92 #size-cells = <0>;
94 ckil: clock@0 {
96 reg = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/scsi/
H A Dmfi.h44 #define MFI_IMSG0 0x10 /* Inbound message 0 */
45 #define MFI_IMSG1 0x14 /* Inbound message 1 */
46 #define MFI_OMSG0 0x18 /* Outbound message 0 */
47 #define MFI_OMSG1 0x1c /* Outbound message 1 */
48 #define MFI_IDB 0x20 /* Inbound doorbell */
49 #define MFI_ISTS 0x24 /* Inbound interrupt status */
50 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
51 #define MFI_ODB 0x2c /* Outbound doorbell */
52 #define MFI_OSTS 0x30 /* Outbound interrupt status */
53 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_device.c25 .chip_ids = ADRENO_CHIP_IDS(0x02000000),
36 .chip_ids = ADRENO_CHIP_IDS(0x02000001),
47 .chip_ids = ADRENO_CHIP_IDS(0x02020000),
59 0x03000512,
60 0x03000520
72 .chip_ids = ADRENO_CHIP_IDS(0x03000600),
84 0x03020000,
85 0x03020001,
86 0x03020002
99 0x03030000,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
[all …]

12