Lines Matching +full:0 +full:x02020000

14 	ldr     r2, =0x02073000		@ r2: target address
28  * This workaround code is relocated to the address 0x02073000
30  * (Base Address - 0x02020000, Limit Address - 0x020740000).
43  * Resume address - 0x2073008
44  * Resume flag - 0x207300C
47  * Switch address - 0x2073018
50  * Hotplug address - 0x207301C
53  * C2 address - 0x2073024
56  * CPU0 state - 0x2073028
57  * CPU1 state - 0x207302C
58  * CPU2 state - 0x2073030
59  * CPU3 state - 0x2073034
62  * CPU0 gic state - 0x2073038
63  * CPU1 gic state - 0x207303C
64  * CPU2 gic state - 0x2073040
65  * CPU3 gic state - 0x2073044
76 	.word   0x0		     @ REG0: RESUME_ADDR
77 	.word   0x0		     @ REG1: RESUME_FLAG
78 	.word   0x0		     @ REG2
79 	.word   0x0		     @ REG3
81 	.word   0x0		     @ REG4: SWITCH_ADDR
83 	.word   0x0		     @ REG5: CPU1_BOOT_REG
84 	.word   0x0		     @ REG6
86 	.word   0x0		     @ REG7: REG_C2_ADDR
88 	.word   0x1		     @ CPU0_STATE : RESET
89 	.word   0x2		     @ CPU1_STATE : SECONDARY RESET
90 	.word   0x2		     @ CPU2_STATE : SECONDARY RESET
91 	.word   0x2		     @ CPU3_STATE : SECONDARY RESET
93 	.word   0x0		     @ CPU0 - GICD_IGROUPR0
94 	.word   0x0		     @ CPU1 - GICD_IGROUPR0
95 	.word   0x0		     @ CPU2 - GICD_IGROUPR0
96 	.word   0x0		     @ CPU3 - GICD_IGROUPR0
99 	mrc     p15, 0, r7, c0, c0, 5   @ read MPIDR
100 	and     r7, r7, #0xf	    @ r7 = cpu id
108 	ldr     r0, =(0x10040000 + 0x804)
110 	cmp     r1, #0x0
111 	movne   r1, #0x0
114 	ldrne   r1, =(0x10040000 + 0x800)
116 	tst     r10, #(1 << 0)
117 	ldrne   pc, =0x23e00000
121 	cmp     r1, #0x0