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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dallwinner,sun4i-a10-lradc-keys.yaml47 "^button-[0-9]+$":
59 enum: [0, 1]
100 reg = <0x01c22800 0x100>;
107 channel = <0>;
114 channel = <0>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-v3s.dtsi72 #size-cells = <0>;
74 cpu@0 {
77 reg = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
126 reg = <0x01000000 0x10000>;
138 reg = <0x01100000 0x100000>;
139 clocks = <&display_clocks 0>,
143 resets = <&display_clocks 0>;
147 #size-cells = <0>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
H A Dsunxi-h3-h5.dtsi87 #clock-cells = <0>;
95 #clock-cells = <0>;
118 reg = <0x01000000 0x10000>;
129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
130 reg = <0x01100000 0x100000>;
139 #size-cells = <0>;
153 reg = <0x01c02000 0x1000>;
163 reg = <0x01c0c000 0x1000>;
172 #size-cells = <0>;
174 tcon0_in: port@0 {
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
H A Dsun6i-a31.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
213 #clock-cells = <0>;
221 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
252 #clock-cells = <0>;
254 reg = <0x01c200d0 0x4>;
274 reg = <0x01c02000 0x1000>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all …]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
71 framebuffer@0 {
97 #clock-cells = <0>;
103 osc32k: clk@0 {
104 #clock-cells = <0>;
119 reg = <0x01c00000 0x30>;
124 sram_a: sram@0 {
126 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi60 simplefb_lcd: framebuffer@0 {
84 #size-cells = <0>;
86 cpu0: cpu@0 {
89 reg = <0>;
105 #clock-cells = <0>;
113 #clock-cells = <0>;
129 reg = <0x01c02000 0x1000>;
138 reg = <0x01c0f000 0x1000>;
152 #size-cells = <0>;
157 reg = <0x01c10000 0x1000>;
[all …]
H A Dsun8i-a83t.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
71 reg = <0>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
155 #clock-cells = <0>;
168 #clock-cells = <0>;
175 #clock-cells = <0>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
195 reg = <0x01c00000 0x30>;
200 sram_a: sram@0 {
202 reg = <0x00000000 0xc000>;
205 ranges = <0 0x00000000 0xc000>;
209 reg = <0x8000 0x4000>;
[all …]
H A Dsun7i-a20.dtsi65 framebuffer@0 {
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
161 reg = <0x40000000 0x80000000>;
184 #clock-cells = <0>;
190 osc32k: clk@0 {
191 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
[all …]
H A Dsun6i-a31.dtsi65 simplefb_hdmi: framebuffer@0 {
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
170 reg = <0x40000000 0x80000000>;
187 #clock-cells = <0>;
192 osc32k: clk@0 {
193 #clock-cells = <0>;
209 #clock-cells = <0>;
216 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-r40.c41 [AW_R40_DEV_SRAM_A1] = 0x00000000,
42 [AW_R40_DEV_SRAM_A2] = 0x00004000,
43 [AW_R40_DEV_SRAM_A3] = 0x00008000,
44 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
45 [AW_R40_DEV_SRAMC] = 0x01c00000,
46 [AW_R40_DEV_EMAC] = 0x01c0b000,
47 [AW_R40_DEV_MMC0] = 0x01c0f000,
48 [AW_R40_DEV_MMC1] = 0x01c10000,
49 [AW_R40_DEV_MMC2] = 0x01c11000,
50 [AW_R40_DEV_MMC3] = 0x01c12000,
[all …]
H A Dallwinner-h3.c38 [AW_H3_DEV_SRAM_A1] = 0x00000000,
39 [AW_H3_DEV_SRAM_A2] = 0x00044000,
40 [AW_H3_DEV_SRAM_C] = 0x00010000,
41 [AW_H3_DEV_SYSCTRL] = 0x01c00000,
42 [AW_H3_DEV_MMC0] = 0x01c0f000,
43 [AW_H3_DEV_SID] = 0x01c14000,
44 [AW_H3_DEV_EHCI0] = 0x01c1a000,
45 [AW_H3_DEV_OHCI0] = 0x01c1a400,
46 [AW_H3_DEV_EHCI1] = 0x01c1b000,
47 [AW_H3_DEV_OHCI1] = 0x01c1b400,
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
124 #clock-cells = <0>;
131 #clock-cells = <0>;
153 #size-cells = <0>;
164 simple-audio-card,dai-link@0 {
175 sound-dai = <&codec 0>;
197 polling-delay-passive = <0>;
198 polling-delay = <0>;
[all …]