arm/dts/sun6i-a31.dtsi

65 		simplefb_hdmi: framebuffer@0 {
100 		#size-cells = <0>;
102 		cpu0: cpu@0 {
105 			reg = <0>;
170 		reg = <0x40000000 0x80000000>;
187 			#clock-cells = <0>;
192 		osc32k: clk@0 {
193 			#clock-cells = <0>;
209 			#clock-cells = <0>;
216 			#clock-cells = <0>;
223 			#clock-cells = <0>;
225 			reg = <0x01c200d0 0x4>;
245 			reg = <0x01c02000 0x1000>;
254 			reg = <0x01c0c000 0x1000>;
268 				#size-cells = <0>;
270 				tcon0_in: port@0 {
272 					#size-cells = <0>;
273 					reg = <0>;
275 					tcon0_in_drc0: endpoint@0 {
276 						reg = <0>;
288 					#size-cells = <0>;
302 			reg = <0x01c0d000 0x1000>;
316 				#size-cells = <0>;
318 				tcon1_in: port@0 {
320 					#size-cells = <0>;
321 					reg = <0>;
323 					tcon1_in_drc0: endpoint@0 {
324 						reg = <0>;
336 					#size-cells = <0>;
350 			reg = <0x01c0f000 0x1000>;
364 			#size-cells = <0>;
369 			reg = <0x01c10000 0x1000>;
383 			#size-cells = <0>;
388 			reg = <0x01c11000 0x1000>;
402 			#size-cells = <0>;
407 			reg = <0x01c12000 0x1000>;
421 			#size-cells = <0>;
426 			reg = <0x01c16000 0x1000>;
432 			clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
441 				#size-cells = <0>;
443 				hdmi_in: port@0 {
445 					#size-cells = <0>;
446 					reg = <0>;
448 					hdmi_in_tcon0: endpoint@0 {
449 						reg = <0>;
461 					#size-cells = <0>;
469 			reg = <0x01c19000 0x0400>;
474 			phys = <&usbphy 0>;
476 			extcon = <&usbphy 0>;
482 			reg = <0x01c19400 0x10>,
483 			      <0x01c1a800 0x4>,
484 			      <0x01c1b800 0x4>;
506 			reg = <0x01c1a000 0x100>;
517 			reg = <0x01c1a400 0x100>;
528 			reg = <0x01c1b000 0x100>;
539 			reg = <0x01c1b400 0x100>;
550 			reg = <0x01c1c400 0x100>;
559 			reg = <0x01c20000 0x400>;
568 			reg = <0x01c20800 0x400>;
580 			gmac_pins_gmii_a: gmac_gmii@0 {
596 			gmac_pins_mii_a: gmac_mii@0 {
605 			gmac_pins_rgmii_a: gmac_rgmii@0 {
618 			i2c0_pins_a: i2c0@0 {
623 			i2c1_pins_a: i2c1@0 {
628 			i2c2_pins_a: i2c2@0 {
644 			mmc0_pins_a: mmc0@0 {
652 			mmc1_pins_a: mmc1@0 {
660 			mmc2_pins_a: mmc2@0 {
688 			spdif_pins_a: spdif@0 {
693 			uart0_pins_a: uart0@0 {
701 			reg = <0x01c20c00 0xa0>;
712 			reg = <0x01c20ca0 0x20>;
716 			#sound-dai-cells = <0>;
718 			reg = <0x01c21000 0x400>;
729 			#sound-dai-cells = <0>;
731 			reg = <0x01c22000 0x400>;
742 			#sound-dai-cells = <0>;
744 			reg = <0x01c22400 0x400>;
756 			reg = <0x01c22800 0x100>;
763 			reg = <0x01c25000 0x100>;
765 			#thermal-sensor-cells = <0>;
770 			reg = <0x01c28000 0x400>;
771 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
783 			reg = <0x01c28400 0x400>;
796 			reg = <0x01c28800 0x400>;
809 			reg = <0x01c28c00 0x400>;
822 			reg = <0x01c29000 0x400>;
835 			reg = <0x01c29400 0x400>;
848 			reg = <0x01c2ac00 0x400>;
854 			#size-cells = <0>;
859 			reg = <0x01c2b000 0x400>;
865 			#size-cells = <0>;
870 			reg = <0x01c2b400 0x400>;
876 			#size-cells = <0>;
881 			reg = <0x01c2b800 0x400>;
887 			#size-cells = <0>;
892 			reg = <0x01c30000 0x1054>;
904 			#size-cells = <0>;
910 			reg = <0x01c15000 0x1000>;
919 			#sound-dai-cells = <0>;
921 			reg = <0x01c22c00 0x400>;
934 			reg = <0x01c60000 0x1000>;
945 			reg = <0x01c68000 0x1000>;
957 			reg = <0x01c69000 0x1000>;
969 			reg = <0x01c6a000 0x1000>;
981 			reg = <0x01c6b000 0x1000>;
993 			reg = <0x01c81000 0x1000>,
994 			      <0x01c82000 0x2000>,
995 			      <0x01c84000 0x2000>,
996 			      <0x01c86000 0x2000>;
1004 			reg = <0x01e00000 0x20000>;
1014 				#size-cells = <0>;
1018 					#size-cells = <0>;
1021 					fe0_out_be0: endpoint@0 {
1022 						reg = <0>;
1036 			reg = <0x01e20000 0x20000>;
1046 				#size-cells = <0>;
1050 					#size-cells = <0>;
1053 					fe1_out_be0: endpoint@0 {
1054 						reg = <0>;
1068 			reg = <0x01e40000 0x10000>;
1081 				#size-cells = <0>;
1083 				be1_in: port@0 {
1085 					#size-cells = <0>;
1086 					reg = <0>;
1088 					be1_in_fe0: endpoint@0 {
1089 						reg = <0>;
1101 					#size-cells = <0>;
1114 			reg = <0x01e50000 0x10000>;
1127 				#size-cells = <0>;
1129 				drc1_in: port@0 {
1131 					#size-cells = <0>;
1132 					reg = <0>;
1142 					#size-cells = <0>;
1145 					drc1_out_tcon0: endpoint@0 {
1146 						reg = <0>;
1160 			reg = <0x01e60000 0x10000>;
1173 				#size-cells = <0>;
1175 				be0_in: port@0 {
1177 					#size-cells = <0>;
1178 					reg = <0>;
1180 					be0_in_fe0: endpoint@0 {
1181 						reg = <0>;
1193 					#size-cells = <0>;
1196 					be0_out_drc0: endpoint@0 {
1197 						reg = <0>;
1206 			reg = <0x01e70000 0x10000>;
1219 				#size-cells = <0>;
1221 				drc0_in: port@0 {
1223 					#size-cells = <0>;
1224 					reg = <0>;
1226 					drc0_in_be0: endpoint@0 {
1227 						reg = <0>;
1234 					#size-cells = <0>;
1237 					drc0_out_tcon0: endpoint@0 {
1238 						reg = <0>;
1252 			reg = <0x01f00000 0x54>;
1261 			reg = <0x01f00c00 0x400>;
1267 			reg = <0x01f01400 0x200>;
1271 				#clock-cells = <0>;
1280 				#clock-cells = <0>;
1289 				#clock-cells = <0>;
1305 				#clock-cells = <0>;
1319 			reg = <0x01f01c00 0x300>;
1328 			reg = <0x01f02000 0x40>;
1334 			reg = <0x01f02c00 0x400>;
1337 			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1339 			resets = <&apb0_rst 0>;
1343 			#size-cells = <0>;
1346 			ir_pins_a: ir@0 {
1359 			reg = <0x01f03400 0x400>;
1365 			pinctrl-0 = <&p2wi_pins>;
1368 			#size-cells = <0>;