Searched +full:0 +full:x010a2000 (Results 1 – 5 of 5) sorted by relevance
42 reg = <0x010a2000 0x1000>,43 <0x010ad000 0x2000>;
26 #define mmGRBM_CNTL_DEFAULT 0x0000001827 #define mmGRBM_SKEW_CNTL_DEFAULT 0x0000002028 #define mmGRBM_STATUS2_DEFAULT 0x0000000029 #define mmGRBM_PWR_CNTL_DEFAULT 0x0000000030 #define mmGRBM_STATUS_DEFAULT 0x0000000031 #define mmGRBM_STATUS_SE0_DEFAULT 0x0000000032 #define mmGRBM_STATUS_SE1_DEFAULT 0x0000000033 #define mmGRBM_SOFT_RESET_DEFAULT 0x0000000034 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x0000010035 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008[all …]
63 #clock-cells = <0>;69 #clock-cells = <0>;75 #size-cells = <0>;77 cpu0: cpu@0 {80 reg = <0x0 0x0>;81 clocks = <&cpufreq_hw 0>;92 qcom,freq-domain = <&cpufreq_hw 0>;109 reg = <0x0 0x100>;110 clocks = <&cpufreq_hw 0>;121 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
30 #clock-cells = <0>;37 #clock-cells = <0>;45 #size-cells = <0>;47 CPU0: cpu@0 {50 reg = <0x0 0x0>;51 clocks = <&cpufreq_hw 0>;56 qcom,freq-domain = <&cpufreq_hw 0>;58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,79 reg = <0x0 0x100>;80 clocks = <&cpufreq_hw 0>;[all …]
77 #clock-cells = <0>;84 #clock-cells = <0>;91 #size-cells = <0>;93 CPU0: cpu@0 {96 reg = <0x0 0x0>;97 clocks = <&cpufreq_hw 0>;101 qcom,freq-domain = <&cpufreq_hw 0>;125 reg = <0x0 0x100>;126 clocks = <&cpufreq_hw 0>;130 qcom,freq-domain = <&cpufreq_hw 0>;[all …]