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/openbmc/linux/include/crypto/
H A Dblake2b.h32 BLAKE2B_IV0 = 0x6A09E667F3BCC908ULL,
33 BLAKE2B_IV1 = 0xBB67AE8584CAA73BULL,
34 BLAKE2B_IV2 = 0x3C6EF372FE94F82BULL,
35 BLAKE2B_IV3 = 0xA54FF53A5F1D36F1ULL,
36 BLAKE2B_IV4 = 0x510E527FADE682D1ULL,
37 BLAKE2B_IV5 = 0x9B05688C2B3E6C1FULL,
38 BLAKE2B_IV6 = 0x1F83D9ABFB41BD6BULL,
39 BLAKE2B_IV7 = 0x5BE0CD19137E2179ULL,
45 state->h[0] = BLAKE2B_IV0 ^ (0x01010000 | keylen << 8 | outlen); in __blake2b_init()
53 state->t[0] = 0; in __blake2b_init()
[all …]
H A Dblake2s.h36 BLAKE2S_IV0 = 0x6A09E667UL,
37 BLAKE2S_IV1 = 0xBB67AE85UL,
38 BLAKE2S_IV2 = 0x3C6EF372UL,
39 BLAKE2S_IV3 = 0xA54FF53AUL,
40 BLAKE2S_IV4 = 0x510E527FUL,
41 BLAKE2S_IV5 = 0x9B05688CUL,
42 BLAKE2S_IV6 = 0x1F83D9ABUL,
43 BLAKE2S_IV7 = 0x5BE0CD19UL,
49 state->h[0] = BLAKE2S_IV0 ^ (0x01010000 | keylen << 8 | outlen); in __blake2s_init()
57 state->t[0] = 0; in __blake2s_init()
[all …]
/openbmc/u-boot/board/warp7/
H A Dimximage.cfg33 DATA 4 0x30340004 0x4F400005
35 DATA 4 0x30391000 0x00000002
36 DATA 4 0x307a0000 0x03040008
37 DATA 4 0x307a0064 0x00200038
38 DATA 4 0x307a0490 0x00000001
39 DATA 4 0x307a00d0 0x00350001
40 DATA 4 0x307a00dc 0x00c3000a
41 DATA 4 0x307a00e0 0x00010000
42 DATA 4 0x307a00e4 0x00110006
43 DATA 4 0x307a00f4 0x0000033f
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_mem_init.c23 0x00000000, 0x00000000, 0x00000000, 0x00000000,
24 0x00000000, 0x00000000, 0x00000000, 0x00000000,
25 0x00000000, 0x00000000, 0x00000000, 0x00000000,
26 0x00000000, 0x00000000, 0x00000000, 0x00000000,
27 0x00000000, 0x00000100, 0x00000000, 0x00000000,
28 0x00000000, 0x00000000, 0x00000000, 0x00000000,
29 0x00000000, 0x00000000, 0x00010101, 0x01010101,
30 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
31 0x00000100, 0x00000100, 0x00000000, 0x00000002,
32 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
[all …]
/openbmc/u-boot/board/sandisk/sansa_fuze_plus/
H A Dspl_boot.c122 0x01010001, 0x00010000, 0x01000000, 0x00000001, in mxs_adjust_memory_params()
123 0x00010101, 0x00000001, 0x00010000, 0x01000001, in mxs_adjust_memory_params()
124 0x01010000, 0x00000001, 0x07000200, 0x04070203, in mxs_adjust_memory_params()
125 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, in mxs_adjust_memory_params()
126 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, in mxs_adjust_memory_params()
127 0x03061323, 0x0000000a, 0x00080008, 0x00200020, in mxs_adjust_memory_params()
128 0x00200020, 0x00200020, 0x000003f7, 0x00000000, in mxs_adjust_memory_params()
129 0x00000000, 0x00000000, 0x00000020, 0x00000000, in mxs_adjust_memory_params()
130 0x001023cd, 0x20410010, 0x00006665, 0x00000000, in mxs_adjust_memory_params()
131 0x00000101, 0x00000001, 0x00000000, 0x00000000, in mxs_adjust_memory_params()
/openbmc/u-boot/board/creative/xfi3/
H A Dspl_boot.c116 0x01010001, 0x00010000, 0x01000000, 0x00000001, in mxs_adjust_memory_params()
117 0x00010101, 0x00000001, 0x00010000, 0x01000001, in mxs_adjust_memory_params()
118 0x01010000, 0x00000001, 0x07000200, 0x04070203, in mxs_adjust_memory_params()
119 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d, in mxs_adjust_memory_params()
120 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313, in mxs_adjust_memory_params()
121 0x03061323, 0x0000000a, 0x00080008, 0x00200020, in mxs_adjust_memory_params()
122 0x00200020, 0x00200020, 0x000003f7, 0x00000000, in mxs_adjust_memory_params()
123 0x00000000, 0x00000000, 0x00000020, 0x00000000, in mxs_adjust_memory_params()
124 0x001023cd, 0x20410010, 0x00006665, 0x00000000, in mxs_adjust_memory_params()
125 0x00000101, 0x00000001, 0x00000000, 0x00000000, in mxs_adjust_memory_params()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c19 #define FSL_SRDSCR0_OFFS 0x0
20 #define FSL_SRDSCR0_DPP_1V2 0x00008800
21 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
22 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
23 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
24 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
25 #define FSL_SRDSCR1_OFFS 0x4
26 #define FSL_SRDSCR1_PLLBW 0x00000040
27 #define FSL_SRDSCR2_OFFS 0x8
28 #define FSL_SRDSCR2_VDD_1V2 0x00800000
[all …]
/openbmc/u-boot/board/freescale/m54418twr/
H A Dm54418twr.c24 return 0; in checkboard()
36 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; in dram_init()
44 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; in dram_init()
46 for (i = 0x13; i < 0x20; i++) { in dram_init()
51 out_8(&pm->pmcr0, 0x2E); in dram_init()
57 out_be32(&sdram->rcrcr, 0x40000000); in dram_init()
58 out_be32(&sdram->padcr, 0x01030203); in dram_init()
60 out_be32(&sdram->cr00, 0x01010101); in dram_init()
61 out_be32(&sdram->cr01, 0x00000101); in dram_init()
62 out_be32(&sdram->cr02, 0x01010100); in dram_init()
[all …]
H A Dsbf_dram_init.S12 move.l #0xFC04002D, %a1
16 move.l #0xEC094060, %a1
17 move.b #0, (%a1)
20 move.l #0xEC09001A, %a1
21 move.w #0xE01D, (%a1)
24 move.l #0xFC0B8180, %a1
25 move.l #0x00000000, (%a1)
26 move.l #0x40000000, (%a1)
28 move.l #0xFC0B81AC, %a1
29 move.l #0x01030203, (%a1)
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dnv04.c28 { 0x00001000, NVKM_ENGINE_GR },
29 { 0x00000100, NVKM_ENGINE_FIFO },
36 nvkm_mask(mc->subdev.device, 0x000200, mask, 0x00000000); in nv04_mc_device_disable()
44 nvkm_mask(device, 0x000200, mask, mask); in nv04_mc_device_enable()
45 nvkm_rd32(device, 0x000200); in nv04_mc_device_enable()
51 return (nvkm_rd32(mc->subdev.device, 0x000200) & mask) == mask; in nv04_mc_device_enabled()
63 { NVKM_ENGINE_DISP , 0, 0, 0x01010000, true },
64 { NVKM_ENGINE_GR , 0, 0, 0x00001000, true },
65 { NVKM_ENGINE_FIFO , 0, 0, 0x00000100 },
66 { NVKM_SUBDEV_BUS , 0, 0, 0x10000000, true },
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-imon-pad.c19 { 0x2a8195b7, KEY_REWIND },
20 { 0x298315b7, KEY_REWIND },
21 { 0x2b8115b7, KEY_FASTFORWARD },
22 { 0x2b8315b7, KEY_FASTFORWARD },
23 { 0x2b9115b7, KEY_PREVIOUS },
24 { 0x298195b7, KEY_NEXT },
26 { 0x2a8115b7, KEY_PLAY },
27 { 0x2a8315b7, KEY_PLAY },
28 { 0x2a9115b7, KEY_PAUSE },
29 { 0x2b9715b7, KEY_STOP },
[all …]
/openbmc/linux/drivers/media/pci/dt3155/
H A Ddt3155.h21 #define DT3155_VER_MIN 0
22 #define DT3155_VER_EXT 0
28 #define EVEN_DMA_START 0x00
29 #define ODD_DMA_START 0x0C
30 #define EVEN_DMA_STRIDE 0x18
31 #define ODD_DMA_STRIDE 0x24
32 #define EVEN_PIXEL_FMT 0x30
33 #define ODD_PIXEL_FMT 0x34
34 #define FIFO_TRIGGER 0x38
35 #define XFER_MODE 0x3C
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,msm8996-pinctrl.yaml65 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
144 reg = <0x01010000 0x300000>;
147 gpio-ranges = <&tlmm 0 0 150>;
/openbmc/u-boot/board/sysam/stmark2/
H A Dsbf_dram_init.S8 .equ PPMCR0, 0xfc04002d
9 .equ MSCR_SDRAMC, 0xec094060
10 .equ MISCCR2, 0xec09001a
11 .equ DDR_RCR, 0xfc0b8180
12 .equ DDR_PADCR, 0xfc0b81ac
13 .equ DDR_CR00, 0xfc0b8000
14 .equ DDR_CR06, 0xfc0b8018
15 .equ DDR_CR09, 0xfc0b8024
16 .equ DDR_CR40, 0xfc0b80a0
17 .equ DDR_CR45, 0xfc0b80b4
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dlcdc.h15 u32 ctrl; /* 0x00 */
16 u32 int0; /* 0x04 */
17 u32 int1; /* 0x08 */
18 u8 res0[0x04]; /* 0x0c */
19 u32 tcon0_frm_ctrl; /* 0x10 */
20 u32 tcon0_frm_seed[6]; /* 0x14 */
21 u32 tcon0_frm_table[4]; /* 0x2c */
22 u8 res1[4]; /* 0x3c */
23 u32 tcon0_ctrl; /* 0x40 */
24 u32 tcon0_dclk; /* 0x44 */
[all …]
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c24 #define NMI_OFF 0
26 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
27 #define TEST_SMM_FLASH_LOCKDOWN 0
35 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); in pch_enable_apic()
37 writel(0, IO_APIC_INDEX); in pch_enable_apic()
46 writel(0, IO_APIC_INDEX); in pch_enable_apic()
48 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic()
55 for (i = 0; i < 3; i++) { in pch_enable_apic()
57 debug(" reg 0x%04x:", i); in pch_enable_apic()
59 debug(" 0x%08x\n", reg32); in pch_enable_apic()
[all …]
/openbmc/linux/arch/powerpc/platforms/4xx/
H A Dpci.c40 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) in ppc440spe_revA()
54 return 0; in ppc440spe_revA()
62 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
83 r->start = r->end = 0; in fixup_ppc4xx_pci_bridge()
84 r->flags = 0; in fixup_ppc4xx_pci_bridge()
103 res->start = 0; in ppc4xx_parse_dma_ranges()
104 size = 0x80000000; in ppc4xx_parse_dma_ranges()
114 while ((rlen -= np * 4) >= 0) { in ppc4xx_parse_dma_ranges()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
17 0x1d191519
18 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-2GB-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
18 0x1d191519
19 0x14040808
[all …]
/openbmc/linux/net/smc/
H A Dsmc_clc.h22 #define SMC_CLC_PROPOSAL 0x01
23 #define SMC_CLC_ACCEPT 0x02
24 #define SMC_CLC_CONFIRM 0x03
25 #define SMC_CLC_DECLINE 0x04
27 #define SMC_TYPE_R 0 /* SMC-R only */
33 #define SMC_CLC_DECL_MEM 0x01010000 /* insufficient memory resources */
34 #define SMC_CLC_DECL_TIMEOUT_CL 0x02010000 /* timeout w4 QP confirm link */
35 #define SMC_CLC_DECL_TIMEOUT_AL 0x02020000 /* timeout w4 QP add link */
36 #define SMC_CLC_DECL_CNFERR 0x03000000 /* configuration error */
37 #define SMC_CLC_DECL_PEERNOSMC 0x03010000 /* peer did not indicate SMC */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]

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