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/openbmc/u-boot/board/freescale/mx53smd/
H A Dimximage.cfg32 DATA 4 0x53fa8554 0x00300000
33 DATA 4 0x53fa8558 0x00300040
34 DATA 4 0x53fa8560 0x00300000
35 DATA 4 0x53fa8564 0x00300040
36 DATA 4 0x53fa8568 0x00300040
37 DATA 4 0x53fa8570 0x00300000
38 DATA 4 0x53fa8574 0x00300000
39 DATA 4 0x53fa8578 0x00300000
40 DATA 4 0x53fa857c 0x00300040
41 DATA 4 0x53fa8580 0x00300040
[all …]
/openbmc/u-boot/board/freescale/mx53ard/
H A Dimximage_dd3.cfg32 DATA 4 0x53fa8554 0x00300000
33 DATA 4 0x53fa8558 0x00300040
34 DATA 4 0x53fa8560 0x00300000
35 DATA 4 0x53fa8564 0x00300040
36 DATA 4 0x53fa8568 0x00300040
37 DATA 4 0x53fa8570 0x00300000
38 DATA 4 0x53fa8574 0x00300000
39 DATA 4 0x53fa8578 0x00300000
40 DATA 4 0x53fa857c 0x00300040
41 DATA 4 0x53fa8580 0x00300040
[all …]
/openbmc/u-boot/board/freescale/mx53loco/
H A Dimximage.cfg32 DATA 4 0x53fa8554 0x00300000
33 DATA 4 0x53fa8558 0x00300040
34 DATA 4 0x53fa8560 0x00300000
35 DATA 4 0x53fa8564 0x00300040
36 DATA 4 0x53fa8568 0x00300040
37 DATA 4 0x53fa8570 0x00300000
38 DATA 4 0x53fa8574 0x00300000
39 DATA 4 0x53fa8578 0x00300000
40 DATA 4 0x53fa857c 0x00300040
41 DATA 4 0x53fa8580 0x00300040
[all …]
/openbmc/u-boot/board/beckhoff/mx53cx9020/
H A Dimximage.cfg30 DATA 4 0x53fa8554 0x00300000
31 DATA 4 0x53fa8558 0x00300040
32 DATA 4 0x53fa8560 0x00300000
33 DATA 4 0x53fa8564 0x00300040
34 DATA 4 0x53fa8568 0x00300040
35 DATA 4 0x53fa8570 0x00300000
36 DATA 4 0x53fa8574 0x00300000
37 DATA 4 0x53fa8578 0x00300000
38 DATA 4 0x53fa857c 0x00300040
39 DATA 4 0x53fa8580 0x00300040
[all …]
/openbmc/u-boot/board/ge/mx53ppd/
H A Dimximage.cfg36 DATA 4 0x53fa8004 0x00194005
37 DATA 4 0x53fa8554 0x00300000
38 DATA 4 0x53fa8558 0x00300040
39 DATA 4 0x53fa8560 0x00300000
40 DATA 4 0x53fa8564 0x00300040
41 DATA 4 0x53fa8568 0x00300040
42 DATA 4 0x53fa8570 0x00300000
43 DATA 4 0x53fa8574 0x00300000
44 DATA 4 0x53fa8578 0x00300000
45 DATA 4 0x53fa857c 0x00300040
[all …]
/openbmc/u-boot/board/inversepath/usbarmory/
H A Dimximage.cfg16 DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
17 DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
18 DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
19 DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
21 DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
22 DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
23 DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
25 DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
26 DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
27 DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
[all …]
/openbmc/u-boot/board/menlo/m53menlo/
H A Dimximage.cfg17 /* Boot Offset 0x400, valid for both SD and NAND boot. */
31 DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
32 DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
33 DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
34 DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
36 DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
37 DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
38 DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
40 DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
41 DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91sam9260.h23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
29 #define ATMEL_ID_USART0 6 /* USART 0 */
34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */
44 #define ATMEL_ID_EMAC0 21 /* Ethernet 0 */
59 #define ATMEL_BASE_TCB0 0xfffa0000
60 #define ATMEL_BASE_TC0 0xfffa0000
61 #define ATMEL_BASE_TC1 0xfffa0040
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9xe.dtsi21 reg = <0x00300000 0x4000>;
24 ranges = <0 0x00300000 0x4000>;
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/u-boot/doc/
H A DREADME.standalone54 x86 0x00040000 0x00040000
55 PowerPC 0x00040000 0x00040004
56 ARM 0x0c100000 0x0c100000
57 MIPS 0x80200000 0x80200000
58 Blackfin 0x00001000 0x00001000
59 NDS32 0x00300000 0x00300000
60 Nios II 0x02000000 0x02000000
61 RISC-V 0x00600000 0x00600000
66 => tftp 0x40000 hello_world.bin
67 => go 0x40004
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME57 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
59 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
60 0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
62 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
64 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
72 0x30000000 - 0x37ffffff : 128MB : NOR flash
73 0x3C000000 - 0x40000000 : 64MB : CPLD
[all …]
/openbmc/u-boot/include/configs/
H A Drk3368_common.h16 #define CONFIG_SYS_SDRAM_BASE 0
17 #define SDRAM_MAX_SIZE 0xff000000
27 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
28 #define CONFIG_SYS_LOAD_ADDR 0x00280000
30 #define CONFIG_SPL_TEXT_BASE 0x00000000
31 #define CONFIG_SPL_MAX_SIZE 0x40000
32 #define CONFIG_SPL_BSS_START_ADDR 0x400000
33 #define CONFIG_SPL_BSS_MAX_SIZE 0x20000
37 "scriptaddr=0x00500000\0" \
38 "pxefile_addr_r=0x00600000\0" \
[all …]
H A Drk3328_common.h17 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
18 #define CONFIG_SYS_LOAD_ADDR 0x00800800
26 #define CONFIG_SYS_SDRAM_BASE 0
27 #define SDRAM_MAX_SIZE 0xff000000
32 "scriptaddr=0x00500000\0" \
33 "pxefile_addr_r=0x00600000\0" \
34 "fdt_addr_r=0x01f00000\0" \
35 "kernel_addr_r=0x02080000\0" \
36 "ramdisk_addr_r=0x04000000\0"
41 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
H A Drk3399_common.h19 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
20 #define CONFIG_SYS_LOAD_ADDR 0x00800800
21 #define CONFIG_SPL_STACK 0xff8effff
22 #define CONFIG_SPL_TEXT_BASE 0xff8c2000
23 #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
25 #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
26 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000
38 #define CONFIG_SYS_SDRAM_BASE 0
39 #define SDRAM_MAX_SIZE 0xf8000000
44 "scriptaddr=0x00500000\0" \
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ralink/
H A Drt288x.h15 #define RT2880_SYSC_BASE IOMEM(0x00300000)
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_ID 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG 0x10
22 #define RT2880_CHIP_NAME0 0x38325452
23 #define RT2880_CHIP_NAME1 0x20203038
25 #define CHIP_ID_ID_MASK 0xff
27 #define CHIP_ID_REV_MASK 0xff
29 #define RT2880_SDRAM_BASE 0x08000000
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5272.h20 #define GPIO_PACNT_PA15MSK (0xC0000000)
21 #define GPIO_PACNT_DGNT1 (0x40000000)
22 #define GPIO_PACNT_PA14MSK (0x30000000)
23 #define GPIO_PACNT_DREQ1 (0x10000000)
24 #define GPIO_PACNT_PA13MSK (0x0C000000)
25 #define GPIO_PACNT_DFSC3 (0x04000000)
26 #define GPIO_PACNT_PA12MSK (0x03000000)
27 #define GPIO_PACNT_DFSC2 (0x01000000)
28 #define GPIO_PACNT_PA11MSK (0x00C00000)
29 #define GPIO_PACNT_QSPI_CS1 (0x00800000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmicrochip,sama5d4-vdec.yaml44 reg = <0x00300000 0x100000>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-msm8994.yaml48 reg = <0x00300000 0x90000>;
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr600_mt47h128m8_3_266_cl5_async.c12 0x00000001,
13 0x00000000,
14 0x01000000,
15 0x00000101,
16 0x00000001,
17 0x01000000,
18 0x00010001,
19 0x00000100,
20 0x00010001,
21 0x00000003,
[all …]
/openbmc/linux/sound/pci/
H A Dsis7019.h17 #define SIS_GCR 0x00
18 #define SIS_GCR_MACRO_POWER_DOWN 0x80000000
19 #define SIS_GCR_MODEM_ENABLE 0x00010000
20 #define SIS_GCR_SOFTWARE_RESET 0x00000001
23 #define SIS_GIER 0x04
24 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000
25 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000
26 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000
27 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000
28 #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1.dtsi38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/openbmc/linux/include/linux/regulator/
H A Dmax8973-regulator.h20 #define MAX8973_CONTROL_REMOTE_SENSE_ENABLE 0x00000001
21 #define MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE 0x00000002
22 #define MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE 0x00000004
23 #define MAX8973_CONTROL_BIAS_ENABLE 0x00000008
24 #define MAX8973_CONTROL_PULL_DOWN_ENABLE 0x00000010
25 #define MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE 0x00000020
27 #define MAX8973_CONTROL_CLKADV_TRIP_DISABLED 0x00000000
28 #define MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US 0x00010000
29 #define MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US 0x00020000
30 #define MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US_HIST_DIS 0x00030000
[all …]

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