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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/openbmc/u-boot/board/gdsys/a38x/
H A Dcontrolcenterdc.c25 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
26 #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
28 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
29 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
30 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
31 #define DB_GP_88F68XX_GPP_POL_MID 0x0
43 return 0; in get_tpm()
53 0x1, /* active interfaces */
55 { { { {0x1, 0, 0, 0},
56 {0x1, 0, 0, 0},
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
17 0x1d191519
18 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-2GB-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
18 0x1d191519
19 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-samsung-4GB-1866.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
18 0x801d181e
19 0x17050a08
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml33 const: 0
51 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
93 minimum: 0
156 minimum: 0
356 reg = <0x70019000 0x1000>;
369 reg = <0x7001b000 0x1000>;
377 #interconnect-cells = <0>;
379 emc-timings-0 {
382 timing-0 {
[all …]
/openbmc/linux/drivers/video/fbdev/riva/
H A Driva_tbl.h55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
[all …]
/openbmc/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_dec_hw.c30 #define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
33 MTK_JPEG_COLOR_420 = 0x00221111,
34 MTK_JPEG_COLOR_422 = 0x00211111,
35 MTK_JPEG_COLOR_444 = 0x00111111,
36 MTK_JPEG_COLOR_422V = 0x00121111,
37 MTK_JPEG_COLOR_422X2 = 0x00412121,
38 MTK_JPEG_COLOR_422VX2 = 0x00222121,
39 MTK_JPEG_COLOR_400 = 0x00110000
57 return 0; in mtk_jpeg_verify_align()
62 param->src_color = (param->sampling_w[0] << 20) | in mtk_jpeg_decide_format()
[all …]
/openbmc/linux/include/crypto/
H A Daria.h42 0x00636363, 0x007c7c7c, 0x00777777, 0x007b7b7b,
43 0x00f2f2f2, 0x006b6b6b, 0x006f6f6f, 0x00c5c5c5,
44 0x00303030, 0x00010101, 0x00676767, 0x002b2b2b,
45 0x00fefefe, 0x00d7d7d7, 0x00ababab, 0x00767676,
46 0x00cacaca, 0x00828282, 0x00c9c9c9, 0x007d7d7d,
47 0x00fafafa, 0x00595959, 0x00474747, 0x00f0f0f0,
48 0x00adadad, 0x00d4d4d4, 0x00a2a2a2, 0x00afafaf,
49 0x009c9c9c, 0x00a4a4a4, 0x00727272, 0x00c0c0c0,
50 0x00b7b7b7, 0x00fdfdfd, 0x00939393, 0x00262626,
51 0x00363636, 0x003f3f3f, 0x00f7f7f7, 0x00cccccc,
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
[all …]
/openbmc/linux/crypto/
H A Dcamellia_generic.c21 0x70707000, 0x82828200, 0x2c2c2c00, 0xececec00,
22 0xb3b3b300, 0x27272700, 0xc0c0c000, 0xe5e5e500,
23 0xe4e4e400, 0x85858500, 0x57575700, 0x35353500,
24 0xeaeaea00, 0x0c0c0c00, 0xaeaeae00, 0x41414100,
25 0x23232300, 0xefefef00, 0x6b6b6b00, 0x93939300,
26 0x45454500, 0x19191900, 0xa5a5a500, 0x21212100,
27 0xededed00, 0x0e0e0e00, 0x4f4f4f00, 0x4e4e4e00,
28 0x1d1d1d00, 0x65656500, 0x92929200, 0xbdbdbd00,
29 0x86868600, 0xb8b8b800, 0xafafaf00, 0x8f8f8f00,
30 0x7c7c7c00, 0xebebeb00, 0x1f1f1f00, 0xcecece00,
[all …]
/openbmc/linux/drivers/media/pci/cx88/
H A Dcx88-cards.c19 static unsigned int tuner[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
20 static unsigned int radio[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
21 static unsigned int card[] = {[0 ... (CX88_MAXBOARDS - 1)] = UNSET };
43 } while (0)
60 .vmux = 0,
81 .vmux = 0,
82 .gpio0 = 0xff00, // internal decoder
85 .vmux = 0,
86 .gpio0 = 0xff01, // mono from tuner chip
90 .gpio0 = 0xff02,
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5433.c50 #define ISP_PLL_LOCK 0x0000
51 #define AUD_PLL_LOCK 0x0004
52 #define ISP_PLL_CON0 0x0100
53 #define ISP_PLL_CON1 0x0104
54 #define ISP_PLL_FREQ_DET 0x0108
55 #define AUD_PLL_CON0 0x0110
56 #define AUD_PLL_CON1 0x0114
57 #define AUD_PLL_CON2 0x0118
58 #define AUD_PLL_FREQ_DET 0x011c
59 #define MUX_SEL_TOP0 0x0200
[all …]