183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
260083261SDirk Eibach /*
360083261SDirk Eibach * Copyright (C) 2015 Stefan Roese <sr@denx.de>
460083261SDirk Eibach * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
560083261SDirk Eibach */
660083261SDirk Eibach
760083261SDirk Eibach #include <common.h>
860083261SDirk Eibach #include <dm.h>
960083261SDirk Eibach #include <miiphy.h>
10d677bfe2SMiquel Raynal #include <tpm-v1.h>
1160083261SDirk Eibach #include <asm/io.h>
1260083261SDirk Eibach #include <asm/arch/cpu.h>
1360083261SDirk Eibach #include <asm-generic/gpio.h>
1460083261SDirk Eibach
152b4ffbf6SChris Packham #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
1660083261SDirk Eibach #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
1760083261SDirk Eibach
1860083261SDirk Eibach #include "keyprogram.h"
1960083261SDirk Eibach #include "dt_helpers.h"
2060083261SDirk Eibach #include "hydra.h"
2160083261SDirk Eibach #include "ihs_phys.h"
2260083261SDirk Eibach
2360083261SDirk Eibach DECLARE_GLOBAL_DATA_PTR;
2460083261SDirk Eibach
2560083261SDirk Eibach #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
2660083261SDirk Eibach #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
2760083261SDirk Eibach
2860083261SDirk Eibach #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
2960083261SDirk Eibach #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
3060083261SDirk Eibach #define DB_GP_88F68XX_GPP_POL_LOW 0x0
3160083261SDirk Eibach #define DB_GP_88F68XX_GPP_POL_MID 0x0
3260083261SDirk Eibach
get_tpm(struct udevice ** devp)33abdc7b8aSSimon Glass static int get_tpm(struct udevice **devp)
34abdc7b8aSSimon Glass {
35abdc7b8aSSimon Glass int rc;
36abdc7b8aSSimon Glass
37abdc7b8aSSimon Glass rc = uclass_first_device_err(UCLASS_TPM, devp);
38abdc7b8aSSimon Glass if (rc) {
39abdc7b8aSSimon Glass printf("Could not find TPM (ret=%d)\n", rc);
40abdc7b8aSSimon Glass return CMD_RET_FAILURE;
41abdc7b8aSSimon Glass }
42abdc7b8aSSimon Glass
43abdc7b8aSSimon Glass return 0;
44abdc7b8aSSimon Glass }
45abdc7b8aSSimon Glass
4660083261SDirk Eibach /*
4760083261SDirk Eibach * Define the DDR layout / topology here in the board file. This will
4860083261SDirk Eibach * be used by the DDR3 init code in the SPL U-Boot version to configure
4960083261SDirk Eibach * the DDR3 controller.
5060083261SDirk Eibach */
512b4ffbf6SChris Packham static struct mv_ddr_topology_map ddr_topology_map = {
522b4ffbf6SChris Packham DEBUG_LEVEL_ERROR,
5360083261SDirk Eibach 0x1, /* active interfaces */
5460083261SDirk Eibach /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
5560083261SDirk Eibach { { { {0x1, 0, 0, 0},
5660083261SDirk Eibach {0x1, 0, 0, 0},
5760083261SDirk Eibach {0x1, 0, 0, 0},
5860083261SDirk Eibach {0x1, 0, 0, 0},
5960083261SDirk Eibach {0x1, 0, 0, 0} },
6060083261SDirk Eibach SPEED_BIN_DDR_1600K, /* speed_bin */
612b4ffbf6SChris Packham MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
622b4ffbf6SChris Packham MV_DDR_DIE_CAP_4GBIT, /* mem_size */
63*ebb1a593SChris Packham MV_DDR_FREQ_533, /* frequency */
6401c541e0SChris Packham 0, 0, /* cas_wl cas_l */
65e6f61622SChris Packham MV_DDR_TEMP_LOW, /* temperature */
66e6f61622SChris Packham MV_DDR_TIM_DEFAULT} }, /* timing */
672b4ffbf6SChris Packham BUS_MASK_32BIT, /* Busses mask */
682b4ffbf6SChris Packham MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
692b4ffbf6SChris Packham { {0} }, /* raw spd data */
702b4ffbf6SChris Packham {0} /* timing parameters */
712b4ffbf6SChris Packham
7260083261SDirk Eibach };
7360083261SDirk Eibach
7460083261SDirk Eibach static struct serdes_map serdes_topology_map[] = {
7560083261SDirk Eibach {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
7660083261SDirk Eibach {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
7760083261SDirk Eibach /* SATA tx polarity is inverted */
7860083261SDirk Eibach {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
7960083261SDirk Eibach {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
8060083261SDirk Eibach {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
8160083261SDirk Eibach {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
8260083261SDirk Eibach };
8360083261SDirk Eibach
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)8460083261SDirk Eibach int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
8560083261SDirk Eibach {
8660083261SDirk Eibach *serdes_map_array = serdes_topology_map;
8760083261SDirk Eibach *count = ARRAY_SIZE(serdes_topology_map);
8860083261SDirk Eibach return 0;
8960083261SDirk Eibach }
9060083261SDirk Eibach
board_pex_config(void)9160083261SDirk Eibach void board_pex_config(void)
9260083261SDirk Eibach {
9360083261SDirk Eibach #ifdef CONFIG_SPL_BUILD
9460083261SDirk Eibach uint k;
9560083261SDirk Eibach struct gpio_desc gpio = {};
9660083261SDirk Eibach
9760083261SDirk Eibach if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
9860083261SDirk Eibach /* prepare FPGA reconfiguration */
9960083261SDirk Eibach dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
10060083261SDirk Eibach dm_gpio_set_value(&gpio, 0);
10160083261SDirk Eibach
10260083261SDirk Eibach /* give lunatic PCIe clock some time to stabilize */
10360083261SDirk Eibach mdelay(500);
10460083261SDirk Eibach
10560083261SDirk Eibach /* start FPGA reconfiguration */
10660083261SDirk Eibach dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
10760083261SDirk Eibach }
10860083261SDirk Eibach
10960083261SDirk Eibach /* wait for FPGA done */
11060083261SDirk Eibach if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
11160083261SDirk Eibach for (k = 0; k < 20; ++k) {
11260083261SDirk Eibach if (dm_gpio_get_value(&gpio)) {
11360083261SDirk Eibach printf("FPGA done after %u rounds\n", k);
11460083261SDirk Eibach break;
11560083261SDirk Eibach }
11660083261SDirk Eibach mdelay(100);
11760083261SDirk Eibach }
11860083261SDirk Eibach }
11960083261SDirk Eibach
12060083261SDirk Eibach /* disable FPGA reset */
12160083261SDirk Eibach if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
12260083261SDirk Eibach dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
12360083261SDirk Eibach dm_gpio_set_value(&gpio, 1);
12460083261SDirk Eibach }
12560083261SDirk Eibach
12660083261SDirk Eibach /* wait for FPGA ready */
12760083261SDirk Eibach if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
12860083261SDirk Eibach for (k = 0; k < 2; ++k) {
12960083261SDirk Eibach if (!dm_gpio_get_value(&gpio))
13060083261SDirk Eibach break;
13160083261SDirk Eibach mdelay(100);
13260083261SDirk Eibach }
13360083261SDirk Eibach }
13460083261SDirk Eibach #endif
13560083261SDirk Eibach }
13660083261SDirk Eibach
mv_ddr_topology_map_get(void)1372b4ffbf6SChris Packham struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
13860083261SDirk Eibach {
13960083261SDirk Eibach return &ddr_topology_map;
14060083261SDirk Eibach }
14160083261SDirk Eibach
board_early_init_f(void)14260083261SDirk Eibach int board_early_init_f(void)
14360083261SDirk Eibach {
14460083261SDirk Eibach #ifdef CONFIG_SPL_BUILD
14560083261SDirk Eibach /* Configure MPP */
14660083261SDirk Eibach writel(0x00111111, MVEBU_MPP_BASE + 0x00);
14760083261SDirk Eibach writel(0x40040000, MVEBU_MPP_BASE + 0x04);
14860083261SDirk Eibach writel(0x00466444, MVEBU_MPP_BASE + 0x08);
14960083261SDirk Eibach writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
15060083261SDirk Eibach writel(0x44400000, MVEBU_MPP_BASE + 0x10);
15160083261SDirk Eibach writel(0x20000334, MVEBU_MPP_BASE + 0x14);
15260083261SDirk Eibach writel(0x40000000, MVEBU_MPP_BASE + 0x18);
15360083261SDirk Eibach writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
15460083261SDirk Eibach
15560083261SDirk Eibach /* Set GPP Out value */
15660083261SDirk Eibach writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
15760083261SDirk Eibach writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
15860083261SDirk Eibach
15960083261SDirk Eibach /* Set GPP Polarity */
16060083261SDirk Eibach writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
16160083261SDirk Eibach writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
16260083261SDirk Eibach
16360083261SDirk Eibach /* Set GPP Out Enable */
16460083261SDirk Eibach writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
16560083261SDirk Eibach writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
16660083261SDirk Eibach #endif
16760083261SDirk Eibach
16860083261SDirk Eibach return 0;
16960083261SDirk Eibach }
17060083261SDirk Eibach
board_init(void)17160083261SDirk Eibach int board_init(void)
17260083261SDirk Eibach {
17360083261SDirk Eibach /* Address of boot parameters */
17460083261SDirk Eibach gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
17560083261SDirk Eibach
17660083261SDirk Eibach return 0;
17760083261SDirk Eibach }
17860083261SDirk Eibach
17960083261SDirk Eibach #ifndef CONFIG_SPL_BUILD
init_host_phys(struct mii_dev * bus)18060083261SDirk Eibach void init_host_phys(struct mii_dev *bus)
18160083261SDirk Eibach {
18260083261SDirk Eibach uint k;
18360083261SDirk Eibach
18460083261SDirk Eibach for (k = 0; k < 2; ++k) {
18560083261SDirk Eibach struct phy_device *phydev;
18660083261SDirk Eibach
18760083261SDirk Eibach phydev = phy_find_by_mask(bus, 1 << k,
18860083261SDirk Eibach PHY_INTERFACE_MODE_SGMII);
18960083261SDirk Eibach
19060083261SDirk Eibach if (phydev)
19160083261SDirk Eibach phy_config(phydev);
19260083261SDirk Eibach }
19360083261SDirk Eibach }
19460083261SDirk Eibach
ccdc_eth_init(void)19560083261SDirk Eibach int ccdc_eth_init(void)
19660083261SDirk Eibach {
19760083261SDirk Eibach uint k;
19860083261SDirk Eibach uint octo_phy_mask = 0;
19960083261SDirk Eibach int ret;
20060083261SDirk Eibach struct mii_dev *bus;
20160083261SDirk Eibach
20260083261SDirk Eibach /* Init SoC's phys */
20360083261SDirk Eibach bus = miiphy_get_dev_by_name("ethernet@34000");
20460083261SDirk Eibach
20560083261SDirk Eibach if (bus)
20660083261SDirk Eibach init_host_phys(bus);
20760083261SDirk Eibach
20860083261SDirk Eibach bus = miiphy_get_dev_by_name("ethernet@70000");
20960083261SDirk Eibach
21060083261SDirk Eibach if (bus)
21160083261SDirk Eibach init_host_phys(bus);
21260083261SDirk Eibach
21360083261SDirk Eibach /* Init octo phys */
21460083261SDirk Eibach octo_phy_mask = calculate_octo_phy_mask();
21560083261SDirk Eibach
21660083261SDirk Eibach printf("IHS PHYS: %08x", octo_phy_mask);
21760083261SDirk Eibach
21860083261SDirk Eibach ret = init_octo_phys(octo_phy_mask);
21960083261SDirk Eibach
22060083261SDirk Eibach if (ret)
22160083261SDirk Eibach return ret;
22260083261SDirk Eibach
22360083261SDirk Eibach printf("\n");
22460083261SDirk Eibach
22560083261SDirk Eibach if (!get_fpga()) {
22660083261SDirk Eibach puts("fpga was NULL\n");
22760083261SDirk Eibach return 1;
22860083261SDirk Eibach }
22960083261SDirk Eibach
23060083261SDirk Eibach /* reset all FPGA-QSGMII instances */
23160083261SDirk Eibach for (k = 0; k < 80; ++k)
23260083261SDirk Eibach writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
23360083261SDirk Eibach
23460083261SDirk Eibach udelay(100);
23560083261SDirk Eibach
23660083261SDirk Eibach for (k = 0; k < 80; ++k)
23760083261SDirk Eibach writel(0, get_fpga()->qsgmii_port_state[k]);
23860083261SDirk Eibach return 0;
23960083261SDirk Eibach }
24060083261SDirk Eibach
24160083261SDirk Eibach #endif
24260083261SDirk Eibach
board_late_init(void)24360083261SDirk Eibach int board_late_init(void)
24460083261SDirk Eibach {
24560083261SDirk Eibach #ifndef CONFIG_SPL_BUILD
24660083261SDirk Eibach hydra_initialize();
24760083261SDirk Eibach #endif
24860083261SDirk Eibach return 0;
24960083261SDirk Eibach }
25060083261SDirk Eibach
board_fix_fdt(void * rw_fdt_blob)25160083261SDirk Eibach int board_fix_fdt(void *rw_fdt_blob)
25260083261SDirk Eibach {
25360083261SDirk Eibach struct udevice *bus = NULL;
25460083261SDirk Eibach uint k;
25560083261SDirk Eibach char name[64];
25660083261SDirk Eibach int err;
25760083261SDirk Eibach
25860083261SDirk Eibach err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
25960083261SDirk Eibach
26060083261SDirk Eibach if (err) {
26160083261SDirk Eibach printf("Could not get I2C bus.\n");
26260083261SDirk Eibach return err;
26360083261SDirk Eibach }
26460083261SDirk Eibach
26560083261SDirk Eibach for (k = 0x21; k <= 0x26; k++) {
26660083261SDirk Eibach snprintf(name, 64,
26760083261SDirk Eibach "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
26860083261SDirk Eibach
26960083261SDirk Eibach if (!dm_i2c_simple_probe(bus, k))
27060083261SDirk Eibach fdt_disable_by_ofname(rw_fdt_blob, name);
27160083261SDirk Eibach }
27260083261SDirk Eibach
27360083261SDirk Eibach return 0;
27460083261SDirk Eibach }
27560083261SDirk Eibach
last_stage_init(void)27660083261SDirk Eibach int last_stage_init(void)
27760083261SDirk Eibach {
278abdc7b8aSSimon Glass struct udevice *tpm;
279abdc7b8aSSimon Glass int ret;
280abdc7b8aSSimon Glass
28160083261SDirk Eibach #ifndef CONFIG_SPL_BUILD
28260083261SDirk Eibach ccdc_eth_init();
28360083261SDirk Eibach #endif
284abdc7b8aSSimon Glass ret = get_tpm(&tpm);
285abdc7b8aSSimon Glass if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
286abdc7b8aSSimon Glass tpm_continue_self_test(tpm)) {
28760083261SDirk Eibach return 1;
28860083261SDirk Eibach }
28960083261SDirk Eibach
29060083261SDirk Eibach mdelay(37);
29160083261SDirk Eibach
292abdc7b8aSSimon Glass flush_keys(tpm);
293abdc7b8aSSimon Glass load_and_run_keyprog(tpm);
29460083261SDirk Eibach
29560083261SDirk Eibach return 0;
29660083261SDirk Eibach }
297