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/openbmc/linux/arch/arm/include/debug/
H A Dsa1100.S10 #define UTCR3 0x0c
11 #define UTDR 0x14
12 #define UTSR1 0x20
13 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
14 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
15 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
18 mrc p15, 0, \rp, c1, c0
20 moveq \rp, #0x80000000 @ physical base address
21 movne \rp, #0xf8000000 @ virtual address
28 add \rp, \rp, #0x00050000
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi10 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
14 #clock-cells = <0>;
20 reg = <0x58400000 0x00050000>;
39 reg = <0x58450000 0x00050000>;
59 reg = <0x585d0000 0x10000>;
71 reg = <0x585f0000 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx8-jpeg.yaml64 reg = <0x58400000 0x00050000 >;
78 reg = <0x58450000 0x00050000 >;
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dsdram.c35 .sdram_config_init = 0x80800EBA,
36 .sdram_config = 0x808022BA,
37 .ref_ctrl = 0x0000081A,
38 .sdram_tim1 = 0x772F6873,
39 .sdram_tim2 = 0x304a129a,
40 .sdram_tim3 = 0x02f7e45f,
41 .read_idle_ctrl = 0x00050000,
42 .zq_config = 0x000b3215,
43 .temp_alert_config = 0x08000a05,
44 .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
[all …]
/openbmc/u-boot/board/ti/dra7xx/
H A Devm.c41 (strncmp("H", board_ti_get_rev(), 1) <= 0))
43 (strncmp("C", board_ti_get_rev(), 1) <= 0))
63 .sdram_config_init = 0x61851ab2,
64 .sdram_config = 0x61851ab2,
65 .sdram_config2 = 0x08000000,
66 .ref_ctrl = 0x000040F1,
67 .ref_ctrl_final = 0x00001035,
68 .sdram_tim1 = 0xCCCF36B3,
69 .sdram_tim2 = 0x308F7FDA,
70 .sdram_tim3 = 0x427F88A8,
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/openbmc/qemu/tests/tcg/tricore/asm/
H A Dtest_imask.S5 # res[31:0]
8 TEST_E_IDI(imask, 1, 0x000f0000, 0x00050000, 0x5, 0x10, 0x4)
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dspl.c15 .dmm_lisa_map_3 = 0x80740300,
16 .is_ma_present = 0x1
25 0x80640100; in emif_get_dmm_regs()
30 .sdram_config_init = 0x61852332,
31 .sdram_config = 0x61852332,
32 .sdram_config2 = 0x00000000,
33 .ref_ctrl = 0x000040f1,
34 .ref_ctrl_final = 0x00001040,
35 .sdram_tim1 = 0xeeef36f3,
36 .sdram_tim2 = 0x348f7fda,
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h16 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
17 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
18 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
19 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
20 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
21 #define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
22 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
23 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
24 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
25 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
[all …]
/openbmc/u-boot/board/ti/am43xx/
H A Dboard.c121 0x00500050,
122 0x00350035,
123 0x00350035,
124 0x00350035,
125 0x00350035,
126 0x00350035,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
[all …]
/openbmc/u-boot/board/compulab/cm_t54/
H A Dspl.c14 .sdram_config_init = 0x618522B2,
15 .sdram_config = 0x618522B2,
17 .sdram_config_init = 0x618522BA,
18 .sdram_config = 0x618522BA,
20 .sdram_config2 = 0x0,
21 .ref_ctrl = 0x00001040,
22 .sdram_tim1 = 0xEEEF36F3,
23 .sdram_tim2 = 0x348F7FDA,
24 .sdram_tim3 = 0x027F88A8,
25 .read_idle_ctrl = 0x00050000,
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_specs_47x.h11 .pvr_mask = 0xffffffff,
12 .pvr_value = 0x11a52080,
24 .pvr_mask = 0xffff0000,
25 .pvr_value = 0x7ff50000,
37 .pvr_mask = 0xffff0000,
38 .pvr_value = 0x00050000,
50 .pvr_mask = 0xffff0000,
51 .pvr_value = 0x11a50000,
63 .pvr_mask = 0x00000000,
64 .pvr_value = 0x00000000,
/openbmc/linux/drivers/dma/
H A Dfsldma.h19 #define FSL_DMA_MR_CS 0x00000001
20 #define FSL_DMA_MR_CC 0x00000002
21 #define FSL_DMA_MR_CA 0x00000008
22 #define FSL_DMA_MR_EIE 0x00000040
23 #define FSL_DMA_MR_XFE 0x00000020
24 #define FSL_DMA_MR_EOLNIE 0x00000100
25 #define FSL_DMA_MR_EOLSIE 0x00000080
26 #define FSL_DMA_MR_EOSIE 0x00000200
27 #define FSL_DMA_MR_CDSM 0x00000010
28 #define FSL_DMA_MR_CTM 0x00000004
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Dvct.h17 #define REG_GLOBAL_START_ADDR 0xbf800000
18 #define TOP_BASE 0x000c8000
31 #define REG_GLOBAL_START_ADDR 0xbf800000
32 #define TOP_BASE 0x000c8000
45 #define REG_GLOBAL_START_ADDR 0xbdc00000
46 #define TOP_BASE 0x00050000
60 #define PRID_COMP_LEGACY 0x000000
61 #define PRID_COMP_MIPS 0x010000
62 #define PRID_IMP_LX4280 0xc200
63 #define PRID_IMP_VGC 0x9000
/openbmc/linux/drivers/of/unittest-data/
H A Doverlay_common.dtsi19 reg = <0x00000100 0x100>;
50 reg = <0x00000100 0x100>;
60 reg = <0x00000030 0x10>;
64 reg = <0x00000040 0x10>;
72 reg = <0x00030000 0x1000>;
78 reg = <0x00040000 0x1000>;
84 reg = <0x00050000 0x1000>;
/openbmc/linux/include/uapi/linux/genwqe/
H A Dgenwqe_card.h36 #define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */
37 #define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */
38 #define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */
39 #define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */
43 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0)
49 #define IO_EXTENDED_ERROR_POINTER 0x00000048
50 #define IO_ERROR_INJECT_SELECTOR 0x00000060
51 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070
52 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078
53 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3))
[all …]
/openbmc/u-boot/arch/x86/include/asm/fsp/
H A Dfsp_fv.h11 #define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
12 #define EFI_FV_FILE_ATTR_FIXED 0x00000100
13 #define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
16 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
17 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
18 #define EFI_FVB2_READ_STATUS 0x00000004
19 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
20 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
21 #define EFI_FVB2_WRITE_STATUS 0x00000020
22 #define EFI_FVB2_LOCK_CAP 0x00000040
[all …]
/openbmc/u-boot/board/compulab/cm_t43/
H A Dspl.c29 .emif_sdram_config_ext = 0x0143,
34 .sdram_config = 0x638413B2,
35 .ref_ctrl = 0x00000C30,
36 .sdram_tim1 = 0xEAAAD4DB,
37 .sdram_tim2 = 0x266B7FDA,
38 .sdram_tim3 = 0x107F8678,
39 .read_idle_ctrl = 0x00050000,
40 .zq_config = 0x50074BE4,
41 .temp_alert_config = 0x0,
42 .emif_ddr_phy_ctlr_1 = 0x0E004008,
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/openbmc/linux/net/smc/
H A Dsmc_llc.h18 #define SMC_LLC_FLAG_RESP 0x80
30 SMC_LLC_CONFIRM_LINK = 0x01,
31 SMC_LLC_ADD_LINK = 0x02,
32 SMC_LLC_ADD_LINK_CONT = 0x03,
33 SMC_LLC_DELETE_LINK = 0x04,
34 SMC_LLC_REQ_ADD_LINK = 0x05,
35 SMC_LLC_CONFIRM_RKEY = 0x06,
36 SMC_LLC_TEST_LINK = 0x07,
37 SMC_LLC_CONFIRM_RKEY_CONT = 0x08,
38 SMC_LLC_DELETE_RKEY = 0x09,
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_dma.h10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
[all …]

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