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/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c26 0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451,
27 0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D,
28 0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9,
31 0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99,
32 0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383,
33 0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF,
38 0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E,
39 0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5,
40 0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD,
43 0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dimx_rproc.c28 #define IMX7D_SRC_SCR 0x0C
32 #define IMX7D_SW_M4C_NON_SCLR_RST BIT(0)
46 #define IMX8M_GPR22 0x58
47 #define IMX8M_GPR22_CM7_CPUWAIT BIT(0)
49 /* Address: 0x020D8000 */
50 #define IMX6SX_SRC_SCR 0x00
66 #define IMX_SIP_RPROC 0xC2000005
67 #define IMX_SIP_RPROC_START 0x00
68 #define IMX_SIP_RPROC_STARTED 0x01
69 #define IMX_SIP_RPROC_STOP 0x02
[all …]
/openbmc/linux/sound/pci/
H A Dsis7019.h17 #define SIS_GCR 0x00
18 #define SIS_GCR_MACRO_POWER_DOWN 0x80000000
19 #define SIS_GCR_MODEM_ENABLE 0x00010000
20 #define SIS_GCR_SOFTWARE_RESET 0x00000001
23 #define SIS_GIER 0x04
24 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000
25 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000
26 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000
27 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000
28 #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000
[all …]
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x18060000,
23 0x08000000,
24 0x00018020,
[all …]
/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x18060000,
23 0x08000000,
24 0x00018020,
[all …]
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dmcf8390.h39 #define NE2000_ADDR 0x40000300
40 #define NE2000_ODDOFFSET 0x00010000
41 #define NE2000_ADDRSIZE 0x00020000
42 #define NE2000_IRQ_VECTOR 0xf0
49 #define NE2000_ADDR 0x40000300
50 #define NE2000_ODDOFFSET 0x00010000
51 #define NE2000_ADDRSIZE 0x00020000
52 #define NE2000_IRQ_VECTOR 0x1c
59 #define NE2000_ADDR 0x30000300
60 #define NE2000_ADDRSIZE 0x00001000
[all …]
/openbmc/u-boot/include/
H A Dfsl_dspi.h16 u32 mcr; /* 0x00 */
17 u32 resv0; /* 0x04 */
18 u32 tcr; /* 0x08 */
19 u32 ctar[8]; /* 0x0C - 0x28 */
20 u32 sr; /* 0x2C */
21 u32 irsr; /* 0x30 */
22 u32 tfr; /* 0x34 - PUSHR */
23 u32 rfr; /* 0x38 - POPR */
25 u32 tfdr[4]; /* 0x3C */
26 u8 resv2[0x30]; /* 0x40 */
[all …]
/openbmc/linux/drivers/net/ethernet/renesas/
H A Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
/openbmc/u-boot/board/sr1500/qts/
H A Diocsr_config.h15 0x00100000,
16 0x40000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x000E0180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Ddspi.h14 u32 mcr; /* 0x00 */
15 u32 resv0; /* 0x04 */
16 u32 tcr; /* 0x08 */
17 u32 ctar[8]; /* 0x0C - 0x28 */
18 u32 sr; /* 0x2C */
19 u32 irsr; /* 0x30 */
20 u32 tfr; /* 0x34 - PUSHR */
21 u16 resv1; /* 0x38 */
22 u16 rfr; /* 0x3A - POPR */
24 u32 tfdr[4]; /* 0x3C */
[all …]
/openbmc/u-boot/include/configs/
H A Dedb93xx.h38 #define CONFIG_ENV_SECT_SIZE 0x00020000
42 #define CONFIG_ENV_SECT_SIZE 0x00020000
46 #define CONFIG_ENV_SECT_SIZE 0x00020000
50 #define CONFIG_ENV_SECT_SIZE 0x00040000
54 #define CONFIG_ENV_SECT_SIZE 0x00020000
58 #define CONFIG_ENV_SECT_SIZE 0x00040000
62 #define CONFIG_ENV_SECT_SIZE 0x00040000
66 #define CONFIG_ENV_SECT_SIZE 0x00020000
83 #define CONFIG_SYS_SERIAL0 0x808C0000
84 #define CONFIG_SYS_SERIAL1 0x808D0000
[all …]
/openbmc/u-boot/board/terasic/sockit/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dkeylargo.h10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72-evm-common.dtsi129 #size-cells = <0>;
131 port@0 {
132 reg = <0>;
194 #clock-cells = <0>;
202 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
203 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
209 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
210 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
221 reg = <0x20>;
230 reg = <0x21>;
[all …]
/openbmc/u-boot/board/engicam/common/
H A Dspl.c43 return 0; in board_fit_config_name_match()
45 return 0; in board_fit_config_name_match()
47 return 0; in board_fit_config_name_match()
49 return 0; in board_fit_config_name_match()
51 return 0; in board_fit_config_name_match()
53 return 0; in board_fit_config_name_match()
81 spl_boot_list[0] = boot_dev; in board_boot_order()
92 return 0; in spl_start_uboot()
99 * 0x30 == 40 Ohm
100 * 0x28 == 48 Ohm
[all …]
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dsoc.h20 * the synchronous boot mode is selected. When ASDO is "0" (i.e
24 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
25 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
26 * decoded at 0xf0000000.
35 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
36 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
37 #define EP93XX_CS1_PHYS_BASE 0x10000000
38 #define EP93XX_CS2_PHYS_BASE 0x20000000
39 #define EP93XX_CS3_PHYS_BASE 0x30000000
40 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]

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