28 #define IMX7D_SRC_SCR			0x0C
32 #define IMX7D_SW_M4C_NON_SCLR_RST	BIT(0)
46 #define IMX8M_GPR22			0x58
47 #define IMX8M_GPR22_CM7_CPUWAIT		BIT(0)
49 /* Address: 0x020D8000 */
50 #define IMX6SX_SRC_SCR			0x00
66 #define IMX_SIP_RPROC			0xC2000005
67 #define IMX_SIP_RPROC_START		0x00
68 #define IMX_SIP_RPROC_STARTED		0x01
69 #define IMX_SIP_RPROC_STOP		0x02
90 #define ATT_CORE_MASK   0xffff
125 	{ 0x0FFC0000, 0x201C0000, 0x00020000, ATT_OWN | ATT_IOMEM },
126 	{ 0x0FFE0000, 0x201E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
129 	{ 0x1FFC0000, 0x201C0000, 0x00020000, ATT_OWN | ATT_IOMEM },
130 	{ 0x1FFE0000, 0x201E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
133 	{ 0x20000000, 0x20200000, 0x00020000, ATT_OWN | ATT_IOMEM },
134 	{ 0x20020000, 0x20220000, 0x00020000, ATT_OWN | ATT_IOMEM },
137 	{ 0x30000000, 0x20200000, 0x00020000, ATT_OWN | ATT_IOMEM },
138 	{ 0x30020000, 0x20220000, 0x00020000, ATT_OWN | ATT_IOMEM },
141 	{ 0x80000000, 0x80000000, 0x10000000, 0 },
142 	{ 0x90000000, 0x80000000, 0x10000000, 0 },
144 	{ 0xC0000000, 0xC0000000, 0x10000000, 0 },
145 	{ 0xD0000000, 0xC0000000, 0x10000000, 0 },
150 	{ 0x08000000, 0x08000000, 0x10000000, 0},
152 	{ 0x1FFE0000, 0x34FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
153 	{ 0x1FFE0000, 0x38FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
155 	{ 0x20000000, 0x35000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
156 	{ 0x20000000, 0x39000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
158 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
162 	{ 0x08000000, 0x08000000, 0x10000000, 0 },
164 	{ 0x1FFE0000, 0x34FE0000, 0x00040000, ATT_OWN | ATT_IOMEM },
166 	{ 0x21000000, 0x00100000, 0x00018000, 0 },
168 	{ 0x21100000, 0x00100000, 0x00040000, 0 },
170 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
176 	{ 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
178 	{ 0x00180000, 0x00180000, 0x00009000, 0 },
180 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
182 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
184 	{ 0x00940000, 0x00940000, 0x00050000, 0 },
186 	{ 0x08000000, 0x08000000, 0x08000000, 0 },
188 	{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
190 	{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM },
192 	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
194 	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
196 	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
198 	{ 0x20240000, 0x00940000, 0x00040000, ATT_OWN },
200 	{ 0x40000000, 0x40000000, 0x80000000, 0 },
206 	{ 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM},
208 	{ 0x00180000, 0x00180000, 0x00008000, 0 },
210 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
212 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
214 	{ 0x08000000, 0x08000000, 0x08000000, 0 },
216 	{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
218 	{ 0x1FFE0000, 0x007E0000, 0x00020000, ATT_OWN  | ATT_IOMEM},
220 	{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN  | ATT_IOMEM},
222 	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
224 	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
226 	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
228 	{ 0x40000000, 0x40000000, 0x80000000, 0 },
232 	{0x1FFC0000, 0x1FFC0000, 0xC0000, ATT_OWN},
233 	{0x21000000, 0x21000000, 0x10000, ATT_OWN},
234 	{0x80000000, 0x80000000, 0x60000000, 0}
238 	{0x1FFD0000, 0x1FFD0000, 0x30000, ATT_OWN},
239 	{0x20000000, 0x20000000, 0x10000, ATT_OWN},
240 	{0x2F000000, 0x2F000000, 0x20000, ATT_OWN},
241 	{0x2F020000, 0x2F020000, 0x20000, ATT_OWN},
242 	{0x60000000, 0x60000000, 0x40000000, 0}
248 	{ 0x00000000, 0x00180000, 0x00008000, 0 },
250 	{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
252 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
254 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
256 	{ 0x00940000, 0x00940000, 0x00008000, 0 },
258 	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
260 	{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
263 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
265 	{ 0x20200000, 0x00900000, 0x00020000, 0 },
267 	{ 0x20220000, 0x00920000, 0x00020000, 0 },
269 	{ 0x20240000, 0x00940000, 0x00008000, 0 },
271 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
277 	{ 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM },
279 	{ 0x00180000, 0x008F8000, 0x00004000, 0 },
281 	{ 0x00180000, 0x008FC000, 0x00004000, 0 },
283 	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
285 	{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
288 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
290 	{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
292 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
397 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_start()
437 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STOP, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_stop()
464 	for (i = 0; i < dcfg->att_size; i++) {  in imx_rproc_da_to_sys()
469 		 * i.MX8QM has dual general M4_[0,1] cores, M4_0's own entries  in imx_rproc_da_to_sys()
470 		 * has "ATT_CORE(0) & BIT(0)" true, M4_1's own entries has  in imx_rproc_da_to_sys()
484 			return 0;  in imx_rproc_da_to_sys()
488 	dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",  in imx_rproc_da_to_sys()
500 	if (len == 0)  in imx_rproc_da_to_va()
510 	for (i = 0; i < IMX_RPROC_MEM_MAX; i++) {  in imx_rproc_da_to_va()
520 	dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",  in imx_rproc_da_to_va()
543 	return 0;  in imx_rproc_mem_alloc()
552 	return 0;  in imx_rproc_mem_release()
565 	of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);  in imx_rproc_prepare()
566 	while (of_phandle_iterator_next(&it) == 0) {  in imx_rproc_prepare()
602 	return  0;  in imx_rproc_prepare()
613 	return 0;  in imx_rproc_parse_fw()
634 	if (err < 0)  in imx_rproc_kick()
657 	return 0;  in imx_rproc_detach()
705 	int a, b = 0, err, nph;  in imx_rproc_addr_init()
708 	for (a = 0; a < dcfg->att_size; a++) {  in imx_rproc_addr_init()
734 	if (nph <= 0)  in imx_rproc_addr_init()
735 		return 0;  in imx_rproc_addr_init()
738 	for (a = 0; a < nph; a++) {  in imx_rproc_addr_init()
750 		err = of_address_to_resource(node, 0, &res);  in imx_rproc_addr_init()
777 	return 0;  in imx_rproc_addr_init()
786 	return 0;  in imx_rproc_notified_idr_cb()
822 		return 0;  in imx_rproc_xtr_mbox_init()
825 		return 0;  in imx_rproc_xtr_mbox_init()
846 	return 0;  in imx_rproc_xtr_mbox_init()
888 		return 0;  in imx_rproc_partition_notify()
894 	return 0;  in imx_rproc_partition_notify()
909 		return 0;  in imx_rproc_attach_pd()
921 	for (i = 0; i < priv->num_pd; i++) {  in imx_rproc_attach_pd()
937 	return 0;  in imx_rproc_attach_pd()
940 	while (--i >= 0) {  in imx_rproc_attach_pd()
958 		return 0;  in imx_rproc_detach_pd()
960 	for (i = 0; i < priv->num_pd; i++) {  in imx_rproc_detach_pd()
965 	return 0;  in imx_rproc_detach_pd()
982 		return 0;  in imx_rproc_detect_mode()
984 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STARTED, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_detect_mode()
987 		return 0;  in imx_rproc_detect_mode()
1001 			priv->core_index = 0;  in imx_rproc_detect_mode()
1042 		return 0;  in imx_rproc_detect_mode()
1069 			return 0;  in imx_rproc_detect_mode()
1082 	return 0;  in imx_rproc_detect_mode()
1093 		return 0;  in imx_rproc_clk_enable()
1111 	return 0;  in imx_rproc_clk_enable()
1177 	return 0;  in imx_rproc_probe()