Home
last modified time | relevance | path

Searched +full:0 +full:x0001000 (Results 1 – 22 of 22) sorted by relevance

/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria5.dtsi8 /memreserve/ 0x00000000 0x0001000;
29 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5.dtsi8 /memreserve/ 0x00000000 0x0001000;
29 cpu1-start-addr = <0xffd080c4>;
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria5.dtsi8 /memreserve/ 0x00000000 0x0001000;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5.dtsi8 /memreserve/ 0x00000000 0x0001000;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml46 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
53 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
63 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
74 normally mapped to the 0x0 address of this region, while eDMA
75 is available at 0x80000 base address.
140 pattern: '^dma([0-9]|1[0-5])?$'
175 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
176 <0xdfc01000 0x0001000>, /* IP registers 2 */
177 <0xd0000000 0x2000000>; /* Configuration space */
H A Dsnps,dw-pcie.yaml55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
83 normally mapped to the 0x0 address of this region, while eDMA
84 is available at 0x80000 base address.
149 pattern: '^dma([0-9]|1[0-5])?$'
222 reg = <0xdfc00000 0x0001000>, /* IP registers */
223 <0xd0000000 0x0002000>; /* Configuration space */
227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/riscv/sifive/u74/
H A Dinstructions.json4 "EventCode": "0x0000100",
9 "EventCode": "0x0000200",
14 "EventCode": "0x0000400",
19 "EventCode": "0x0000800",
24 "EventCode": "0x0001000",
29 "EventCode": "0x0002000",
34 "EventCode": "0x0004000",
39 "EventCode": "0x0008000",
44 "EventCode": "0x0010000",
49 "EventCode": "0x0020000",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-welltech-epbx100.dts16 memory@0 {
19 reg = <0x00000000 0x4000000>;
23 bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M";
33 flash@0,0 {
39 reg = <0 0x00000000 0x1000000>;
46 partition@0 {
48 reg = <0x00000000 0x00080000>;
53 reg = <0x00080000 0x00100000>;
58 reg = <0x00180000 0x00300000>;
63 reg = <0x00480000 0x00b60000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
H A Dhighbank.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
24 reg = <0x900>;
43 reg = <0x901>;
62 reg = <0x902>;
81 reg = <0x903>;
98 memory@0 {
101 reg = <0x00000000 0xff900000>;
105 ranges = <0x00000000 0x00000000 0xffffffff>;
109 reg = <0xfff00000 0x1000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Ddigsy_mtc.dts19 memory@0 {
20 reg = <0x00000000 0x02000000>; // 32MB
57 phy0: ethernet-phy@0 {
58 reg = <0>;
65 reg = <0x50>;
70 reg = <0x56>;
75 reg = <0x68>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
87 0xc000 0 0 2 &mpc5200_pic 0 0 3
[all …]
H A Dmpc836x_rdk.dts32 #size-cells = <0>;
34 PowerPC,8360@0 {
36 reg = <0>;
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
51 reg = <0 0>;
60 ranges = <0 0xe0000000 0x200000>;
61 reg = <0xe0000000 0x200>;
63 bus-frequency = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/openbmc/linux/Documentation/arch/arm/
H A Dmemory.rst66 is equal to 0xff800000.
101 must not access any memory which is not mapped inside their 0x0001000
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_tx_regif.h17 REG_LINK_BW_SET = 0x000,
18 REG_LANE_COUNT_SET = 0x004,
19 REG_ENHANCED_FRAME_EN = 0x008,
20 REG_TRAINING_PATTERN_SET = 0x00C,
21 REG_LINK_QUAL_PATTERN_SET = 0x010,
22 REG_SCRAMBLING_DISABLE = 0x014,
23 REG_DOWNSPREAD_CTRL = 0x018,
24 REG_SOFT_RESET = 0x01C,
29 REG_ENABLE = 0x080,
30 REG_ENABLE_MAIN_STREAM = 0x084,
[all …]
/openbmc/linux/include/sound/
H A Dacp63_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x0000000
13 #define ACP_DMA_CNTL_1 0x0000004
14 #define ACP_DMA_CNTL_2 0x0000008
15 #define ACP_DMA_CNTL_3 0x000000C
16 #define ACP_DMA_CNTL_4 0x0000010
17 #define ACP_DMA_CNTL_5 0x0000014
18 #define ACP_DMA_CNTL_6 0x0000018
19 #define ACP_DMA_CNTL_7 0x000001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
[all …]
/openbmc/qemu/docs/specs/
H A Drocker.rst34 * Use of leading 0x indicates a hexadecimal number.
35 * Use of leading 0b indicates a binary number.
54 0x0 2 Vendor ID 0x1b36
55 0x2 2 Device ID 0x0006
56 0x4 4 Command/Status
57 0x8 1 Revision ID 0x01
58 0x9 3 Class code 0x2800
59 0xC 1 Cache line size
60 0xD 1 Latency timer
61 0xE 1 Header type
[all …]
/openbmc/linux/drivers/net/ethernet/nvidia/
H A Dforcedeth.c66 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet form…
69 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
[all …]